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1. 发明申请

US20120028460A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120028460A1
公开(公告)日：2012-02-02
申请号：US13270668
申请日：2011-10-11
申请人： Makoto WADA , Kazuyuki Higashi
发明人： Makoto WADA , Kazuyuki Higashi
IPC分类号： H01L21/768
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与所述第一导电构件的上表面的一部分接触的第二导电构件; 形成在所述第一绝缘膜上以与所述第一导电构件的所述上表面的一部分接触并且包括除了Si之外的所述第一绝缘膜中包含的元素中的至少一种元素的第二绝缘膜; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

2. 发明授权

US08058730B2 Semiconductor device having a multilayered interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08058730B2
公开(公告)日：2011-11-15
申请号：US12239236
申请日：2008-09-26
申请人： Makoto Wada , Kazuyuki Higashi
发明人： Makoto Wada , Kazuyuki Higashi
IPC分类号： H01L29/06
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与第一导电构件的上表面的一部分接触的第二导电构件，形成在第一绝缘膜上以与第一导电构件的上表面的一部分接触的第二绝缘膜，以及包括除Si之外的第一绝缘膜中包含的元素中的至少一种元素; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

3. 发明申请

US20090206491A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090206491A1
公开(公告)日：2009-08-20
申请号：US12361979
申请日：2009-01-29
申请人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
发明人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

4. 发明授权

US08759162B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08759162B2
公开(公告)日：2014-06-24
申请号：US13172330
申请日：2011-06-29
申请人： Makoto Wada , Kazuyuki Higashi , Naofumi Nakamura , Tsuneo Uenaka
发明人： Makoto Wada , Kazuyuki Higashi , Naofumi Nakamura , Tsuneo Uenaka
IPC分类号： H01L21/8239
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

5. 发明授权

US08022461B2 Semiconductor device and method for fabricating semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08022461B2
公开(公告)日：2011-09-20
申请号：US12468504
申请日：2009-05-19
申请人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
发明人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L29/76
CPC分类号： H01L23/522 , H01L21/76816 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L21/76895 , H01L23/5226 , H01L27/10885 , H01L27/10888 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.
摘要翻译：半导体器件包括在存储器件区域中以相同的线宽和间距重复排列的多个位线; 与多个位线的平行布置在与该多个位线相同层的多个分流线，并且与存储器件区域中的多个位线的线宽和间距相同; 以及从上层侧配置的上层接触插塞，以便通过在两条或多条分路线上延伸而连接到多条分路线。

6. 发明授权

US08759983B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08759983B2
公开(公告)日：2014-06-24
申请号：US12361979
申请日：2009-01-29
申请人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
发明人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L29/41
CPC分类号： H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

7. 发明授权

US07989880B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07989880B2
公开(公告)日：2011-08-02
申请号：US12615598
申请日：2009-11-10
申请人： Makoto Wada , Kazuyuki Higashi , Naofumi Nakamura , Tsuneo Uenaka
发明人： Makoto Wada , Kazuyuki Higashi , Naofumi Nakamura , Tsuneo Uenaka
IPC分类号： H01L29/76
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

8. 发明申请

US20090085214A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090085214A1
公开(公告)日：2009-04-02
申请号：US12239236
申请日：2008-09-26
申请人： Makoto WADA , Kazuyuki Higashi
发明人： Makoto WADA , Kazuyuki Higashi
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与第一导电构件的上表面的一部分接触的第二导电构件，形成在第一绝缘膜上以与第一导电构件的上表面的一部分接触的第二绝缘膜，以及包括除Si之外的第一绝缘膜中包含的元素中的至少一种元素; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

9. 发明授权

US08592890B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08592890B2
公开(公告)日：2013-11-26
申请号：US13004229
申请日：2011-01-11
申请人： Nobutaka Watanabe , Kazuyuki Higashi , Gaku Sudo
发明人： Nobutaka Watanabe , Kazuyuki Higashi , Gaku Sudo
IPC分类号： H01L29/792 , H01L29/76
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.
摘要翻译：根据一个实施例，半导体存储器件包括层叠体，接触部，半导体部件，电荷存储层和穿透部件。层叠体包括与绝缘膜交替堆叠的电极膜。层叠体的端部的结构是具有设置在每个电极膜上的台阶的台阶构造。触点从端部的上方连接到电极膜。半导体构件设置在除了端部之外的层叠体的一部分中，以在层叠方向上刺穿层叠体。电荷存储层设置在电极膜和半导体部件之间。穿透构件在层叠方向上刺穿端部。穿透构件不包含与电荷存储层相同的材料。

10. 发明授权

US08148274B2 Semiconductor device having oxidized metal film and manufacture method of the same 有权
标题翻译：具有氧化金属膜的半导体器件及其制造方法
公开(公告)号：US08148274B2
公开(公告)日：2012-04-03
申请号：US12010372
申请日：2008-01-24
申请人： Junichi Wada , Atsuko Sakata , Seiichi Omoto , Masaaki Hatano , Soichi Yamashita , Kazuyuki Higashi , Naofumi Nakamura , Masaki Yamada , Kazuya Kinoshita , Tomio Katata , Masahiko Hasunuma
发明人： Junichi Wada , Atsuko Sakata , Seiichi Omoto , Masaaki Hatano , Soichi Yamashita , Kazuyuki Higashi , Naofumi Nakamura , Masaki Yamada , Kazuya Kinoshita , Tomio Katata , Masahiko Hasunuma
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31616 , C23C16/045 , C23C16/45536 , C23C16/482 , H01L21/02178 , H01L21/02186 , H01L21/02244 , H01L21/02255 , H01L21/28556 , H01L21/28562 , H01L21/67109 , H01L21/67748 , H01L21/6831 , H01L21/68742 , H01L21/68764 , H01L21/68771 , H01L21/76807 , H01L21/76814 , H01L21/76828 , H01L21/76831 , H01L21/76835 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76874 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
摘要翻译：一种制造半导体器件的方法包括将其上具有绝缘膜的衬底加热到第一衬底温度，使得氧化物质从绝缘膜发射，绝缘膜具有形成在其表面上的凹陷部分，在所述绝缘膜的第二衬底温度低于所述第一衬底温度，并且氧化至少部分所述金属膜的氧化物质残留在所述绝缘膜中。

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