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    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US09029869B2
    • 2015-05-12
    • US13034264
    • 2011-02-24
    • Hiroshi KonoTakashi ShinoheChiharu OtaMakoto MizukamiTakuma SuzukiJohji Nishio
    • Hiroshi KonoTakashi ShinoheChiharu OtaMakoto MizukamiTakuma SuzukiJohji Nishio
    • H01L29/15H01L29/739H01L29/10H01L29/66
    • H01L29/7395H01L29/1033H01L29/66333
    • One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.
    • 半导体器件的一个实施例包括:包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。
    • 4. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US08569795B2
    • 2013-10-29
    • US13217472
    • 2011-08-25
    • Hiroshi KonoYukio NakabayashiTakashi ShinoheMakoto Mizukami
    • Hiroshi KonoYukio NakabayashiTakashi ShinoheMakoto Mizukami
    • H01L33/32H01L29/80H01L29/16H01L27/11H01L27/10
    • H01L29/7802H01L21/049H01L29/0623H01L29/1608H01L29/4236H01L29/45H01L29/4966H01L29/66068H01L29/7813
    • A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.
    • 实施例的半导体器件包括:碳化硅衬底,其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层,所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。
    • 6. 发明授权
    • Semiconductor storage device and manufacturing method thereof
    • 半导体存储装置及其制造方法
    • US07804133B2
    • 2010-09-28
    • US12022382
    • 2008-01-30
    • Takeshi MurataMakoto MizukamiFumitaka Arai
    • Takeshi MurataMakoto MizukamiFumitaka Arai
    • H01L27/115
    • H01L27/105H01L21/84H01L27/11526H01L27/11529H01L27/1203
    • Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.
    • 其中具有不同功能的多个半导体元件器件设置在部分SOI衬底的适当区域中并且每个栅绝缘体和每个栅电极之间的界面形成为相同水平的半导体存储器件,并且其制造方法被公开 。 根据一个方面,提供一种半导体存储装置,包括设置在包括具有开口部分的埋入式绝缘体的半导体衬底中的第一半导体区域,不包括埋入绝缘体的第二半导体区域,设置在掩埋层上方的多个第一半导体元件器件 绝缘体,多个第二半导体元件器件,每个第二半导体元件器件设置在包括所述埋入绝缘体的开口部分上方的区域的区域中,以及设置在所述第二半导体区域中的多个第三半导体元件器件。
    • 8. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20080253183A1
    • 2008-10-16
    • US12061075
    • 2008-04-02
    • Makoto MizukamiKiyohito Nishihara
    • Makoto MizukamiKiyohito Nishihara
    • G11C16/04
    • H01L27/105H01L27/0688H01L27/11529H01L27/11531H01L27/11556
    • A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.
    • 半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底,形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路, 以向存储单元阵列提供电信号。 存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。 第一互连层堆叠在第一上表面上,通过绝缘膜彼此分离,并沿第一方向延伸。 第二互连层向上延伸并且通过绝缘膜彼此分离。
    • 9. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07368783B2
    • 2008-05-06
    • US11230492
    • 2005-09-21
    • Makoto MizukamiTakashi Shinohe
    • Makoto MizukamiTakashi Shinohe
    • H01L29/94
    • H01L29/7813H01L29/0623H01L29/0634H01L29/086H01L29/0878H01L29/66666H01L29/7397H01L29/7811H01L29/7828H01L29/8083
    • A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
    • 半导体器件包括第一导电类型的半导体衬底,形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层,形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上,包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极,形成在所述衬底的所述第二主表面上的第二半导体区, 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层,包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ,形成在第一和第二半导体区域上的第二和第三电极, 分别。