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1. 发明授权

US08346828B2 System and method for storing numbers in first and second formats in a register file 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US08346828B2
公开(公告)日：2013-01-01
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F5/00
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

2. 发明授权

US08032854B2 3-stack floorplan for floating point unit 有权
标题翻译：浮动单元的3层平面布置图
公开(公告)号：US08032854B2
公开(公告)日：2011-10-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译：用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。

3. 发明申请

US20100095099A1 SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS IN A REGISTER FILE 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US20100095099A1
公开(公告)日：2010-04-15
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F9/302 , G06F9/312 , G06F7/38
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

4. 发明申请

US20100058266A1 3-Stack Floorplan for Floating Point Unit 有权
标题翻译：浮点单元3堆叠平面图
公开(公告)号：US20100058266A1
公开(公告)日：2010-03-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译：用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。

5. 发明授权

US08291003B2 Supporting multiple formats in a floating point processor 有权
标题翻译：在浮点处理器中支持多种格式
公开(公告)号：US08291003B2
公开(公告)日：2012-10-16
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译：在二进制浮点处理器中，通过用结果精度（Emin）的最小指数值偏置指数，将各种类型的操作数中的每一个的指数重新编码为内部格式，即指数的重新编码值为指数的代表值减去Emin。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。然后以这种新格式执行指数计算。对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。

6. 发明申请

US20100063987A1 SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR 有权
标题翻译：支持浮点处理器中的多个格式
公开(公告)号：US20100063987A1
公开(公告)日：2010-03-11
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译：在二进制浮点处理器中，通过使用结果精度（“Emin”）的最小指数值偏移指数，即将重新编码的值转换为内部格式，将各种类型的操作数中的每一个的指数重新编码为内部格式指数是指数减去Emin的表示值。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。然后以这种新格式执行指数计算。对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。

7. 发明申请

US20130124588A1 ENCODING DENSELY PACKED DECIMALS 有权
标题翻译：编码密封包装十进制
公开(公告)号：US20130124588A1
公开(公告)日：2013-05-16
申请号：US13296273
申请日：2011-11-15
申请人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
发明人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
IPC分类号： G06F7/483
CPC分类号： G06F7/491 , G06F7/49915 , G06F2207/4911 , G06F2207/4912
摘要： According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.
摘要翻译：根据本公开的一个方面，公开了一种用于编码密集包装小数的方法和技术。该方法包括：执行被配置为以二进制编码十进制（BCD）格式对十进制数据执行浮点运算的浮点指令; 确定所述操作的结果是否包括舍入尾数溢出; 并且响应于确定所述操作的结果包括四舍五入的尾数溢出，通过将所述BCD格式化的十进制数据的所述BCD格式的十进制数据的选择位值移位，以密集的十进制（DPD）格式将所述操作的结果压缩为十进制数据十进制数据以一位数字选择DPD格式的位位置。

8. 发明授权

US09128758B2 Encoding densely packed decimals 有权
标题翻译：编码密集的小数
公开(公告)号：US09128758B2
公开(公告)日：2015-09-08
申请号：US13296273
申请日：2011-11-15
申请人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
发明人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
IPC分类号： G06F7/491 , G06F7/499
CPC分类号： G06F7/491 , G06F7/49915 , G06F2207/4911 , G06F2207/4912
摘要： According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.
摘要翻译：根据本公开的一个方面，公开了一种用于编码密集包装小数的方法和技术。该方法包括：执行被配置为以二进制编码十进制（BCD）格式对十进制数据执行浮点运算的浮点指令; 确定所述操作的结果是否包括舍入尾数溢出; 并且响应于确定所述操作的结果包括四舍五入的尾数溢出，通过将所述BCD格式化的十进制数据的所述BCD格式的十进制数据的选择位值移位，以密集的十进制（DPD）格式将所述操作的结果压缩为十进制数据十进制数据以一位数字选择DPD格式的位位置。

9. 发明授权

US07228403B2 Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture 有权
标题翻译：用于处理具有64位架构的乱序处理器的32位结果的方法
公开(公告)号：US07228403B2
公开(公告)日：2007-06-05
申请号：US09683351
申请日：2001-12-18
申请人： Petra Leber , Jens Leenstra , Wolfram Sauer , Dieter Wendel
发明人： Petra Leber , Jens Leenstra , Wolfram Sauer , Dieter Wendel
IPC分类号： G06F9/40 , G06F9/44
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction. The extract instruction includes the steps of dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station, issuing the extract instruction to an Instruction Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme, executing the extract instruction by an available IEU, setting an indication that the result of the instruction needs to be written into the result field of the instruction following the extract instruction, and writing the extract instruction result into the result field of the first instruction, and into all fields of operands being dependent of the first instruction.
摘要翻译：一种用于操作具有较大位长度的架构的处理器的方法，所述程序包括编译为产生至少一个较小位长度的指令结果的指令的程序，所述指令结果具有以下步骤：在程序顺序中检测何时将发送第一较小位长指令，将目标寄存器地址作为其源之一，并在较小的比特长指令之前将so_extract_instruction添加到指令流中。提取指令包括以下步骤：将提取指令与以下较小的比特长指令一起从指令队列发送到预留站，一旦所有源操作数数据可用，就将提取指令发送到指令执行单元（IEU），并且 IEU根据各自的发行方案可用，通过可用的IEU执行提取指令，将提示结果的指示需要写入到提取指令之后的指令的结果字段中，并将提取指令结果写入第一条指令的结果字段，以及依赖于第一条指令的操作数的所有字段。

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