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1. 发明授权

US10318464B1 Memory system and method for accessing memory system 有权
公开(公告)号：US10318464B1
公开(公告)日：2019-06-11
申请号：US16022660
申请日：2018-06-28
申请人： MONTAGE TECHNOLOGY CO., LTD.
发明人： Yibo Jiang , Gang Yan , Robert Xi Jin , Lizhi Jin , Leechung Yiu
IPC分类号： G06F13/16 , G06F13/40
摘要： A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the non-target local controller is configured to provide to the non-target memory ranks, in response to receiving the one or more non-target access CS signals, one or more composite on-die termination (ODT) instructions which instruct respective ones of the one or more non-target memory ranks to selectively switch on non-target DQ/DQS ODT for a data communication bus coupled between the first plurality of memory ranks and the memory controller at least for a period when the memory controller is performing target access to the target memory rank; wherein each composite ODT instruction comprises a combination of secondary CS instruction(s) and a secondary CA instruction.

2. 发明授权

US10579280B2 On-die termination control for memory systems 有权
公开(公告)号：US10579280B2
公开(公告)日：2020-03-03
申请号：US16022650
申请日：2018-06-28
申请人： MONTAGE TECHNOLOGY CO., LTD.
发明人： Yibo Jiang , Gang Yan , Robert Xi Jin , Lizhi Jin , Leechung Yiu
IPC分类号： G06F3/06
摘要： A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the CA signal is being received from the memory controller.

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