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1. 发明申请

US20220029015A1 APPARATUSES COMPRISING VERTICAL TRANSISTORS HAVING GATE ELECTRODES AT LEAST PARTIALLY RECESSED WITHIN CHANNEL REGIONS, AND RELATED METHODS AND SYSTEMS 有权
公开(公告)号：US20220029015A1
公开(公告)日：2022-01-27
申请号：US16936983
申请日：2020-07-23
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Kevin J. Torek , Kamal M. Karda , Yunfei Gao , Kamal K. Muthukrishnan
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L29/66 , H01L21/764 , H01L21/8234 , H01L27/088
摘要： An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.

2. 发明申请

US20190067453A1 METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING THIN FILM TRANSISTORS INCLUDING OXIDE SEMICONDUCTORS 审中-公开
公开(公告)号：US20190067453A1
公开(公告)日：2019-02-28
申请号：US16114614
申请日：2018-08-28
申请人： Micron Technology, Inc.
发明人： Kevin J. Torek
IPC分类号： H01L29/66 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/786
摘要： A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

3. 发明授权

US09799658B2 Methods of forming capacitors 有权
公开(公告)号：US09799658B2
公开(公告)日：2017-10-24
申请号：US14931073
申请日：2015-11-03
申请人： Micron Technology, Inc.
发明人： Gurpreet Lugani , Kevin J. Torek
IPC分类号： H01L27/108 , H01L49/02 , H01L21/3065 , H01L21/3213 , H01G4/008 , H01G4/005 , H01G4/06 , H01L21/311
CPC分类号： H01L27/10852 , H01G4/005 , H01G4/008 , H01G4/06 , H01L21/3065 , H01L21/31116 , H01L21/32137 , H01L27/10894 , H01L28/40 , H01L28/60 , H01L28/75 , H01L28/91
摘要： A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

4. 发明授权

US09583381B2 Methods for forming semiconductor devices and semiconductor device structures 有权
标题翻译：用于形成半导体器件和半导体器件结构的方法
公开(公告)号：US09583381B2
公开(公告)日：2017-02-28
申请号：US13918065
申请日：2013-06-14
申请人： Micron Technology, Inc.
发明人： Ranjan Khurana , Michael Hyatt , Scott L. Light , Kevin J. Torek , Anton J. deVilliers
IPC分类号： H01L21/311 , H01L21/312 , H01L21/32 , G03F7/26 , H01L21/768 , H01L21/027 , H01L21/033 , G03F7/095 , G03F7/00 , H01L49/02
CPC分类号： H01L21/76816 , G03F7/0035 , G03F7/095 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L28/90
摘要： Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of a second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.
摘要翻译：在半导体器件结构中形成半导体器件和特征的方法包括进行防间隔工艺以去除第一掩模材料的部分以形成沿第一方向延伸的第一开口。进行另一个防间隔处理以去除第一掩模材料的部分，以形成沿与第一方向成角度的第二方向延伸的第二开口。去除在第一开口和第二开口的交叉点处的第一掩模材料下面的第二掩模材料的部分，以在第二掩模材料中形成孔并暴露第二掩模材料下面的衬底。

5. 发明授权

US11908932B2 Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems 有权
公开(公告)号：US11908932B2
公开(公告)日：2024-02-20
申请号：US16936983
申请日：2020-07-23
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Kevin J. Torek , Kamal M. Karda , Yunfei Gao , Kamal K. Muthukrishnan
IPC分类号： H01L29/78 , H01L29/10 , H01L27/088 , H01L21/8234 , H01L29/06 , H01L21/764 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/764 , H01L21/823481 , H01L21/823487 , H01L27/088 , H01L29/0649 , H01L29/1037 , H01L29/66666
摘要： An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.

6. 发明申请

US20200335405A1 METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING THIN FILM TRANSISTORS INCLUDING OXIDE SEMICONDUCTORS 审中-公开
公开(公告)号：US20200335405A1
公开(公告)日：2020-10-22
申请号：US16917379
申请日：2020-06-30
申请人： Micron Technology, Inc.
发明人： Kevin J. Torek
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/786 , H01L29/423 , H01L21/822 , H01L27/06 , H01L27/108 , H01L21/02 , H01L21/84 , H01L21/308
摘要： A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

7. 发明授权

US09196673B2 Methods of forming capacitors 有权
标题翻译：形成电容器的方法
公开(公告)号：US09196673B2
公开(公告)日：2015-11-24
申请号：US14147895
申请日：2014-01-06
申请人： Micron Technology, Inc.
发明人： Gurpreet Lugani , Kevin J. Torek
IPC分类号： H01L21/20 , H01L21/302 , H01L21/461 , H01L49/02 , H01L27/108 , H01L21/311
CPC分类号： H01L27/10852 , H01G4/005 , H01G4/008 , H01G4/06 , H01L21/3065 , H01L21/31116 , H01L21/32137 , H01L27/10894 , H01L28/40 , H01L28/60 , H01L28/75 , H01L28/91
摘要： A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.
摘要翻译：形成电容器的方法包括在支撑材料内提供第一电容器电极。第一电容器电极含有TiN，载体材料含有多晶硅。使用含硫和含氟蚀刻化学法，相对于含TiN的第一电容器电极，选择性地对含多晶硅的支撑材料进行干式各向异性蚀刻。在第一电容器电极的侧壁上形成电容器电介质，并且在电容器电介质上形成第二电容器电极。公开了另外的方法。

8. 发明申请

US20140162458A1 Methods of Forming A Pattern On A Substrate 有权
标题翻译：在基板上形成图案的方法
公开(公告)号：US20140162458A1
公开(公告)日：2014-06-12
申请号：US13712820
申请日：2012-12-12
申请人： MICRON TECHNOLOGY, INC.
发明人： Ranjan Khurana , Anton J. DeVillers , Kevin J. Torek , Shane J. Trapp , Scott L. Light , James M. Buntin
IPC分类号： H01L21/308 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/0273 , H01L21/0337 , H01L21/22 , H01L21/266 , H01L21/302 , H01L21/31138 , H01L21/31144 , H01L21/32 , H01L21/76816
摘要： A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.
摘要翻译：在衬底上形成图案的方法包括在衬底的材料中形成开口。开口被加宽以与紧邻的开口接合以在扩宽之后形成包括材料的间隔的柱。公开了其他实施例。

9. 发明申请

US20230014320A1 Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors 有权
公开(公告)号：US20230014320A1
公开(公告)日：2023-01-19
申请号：US17947401
申请日：2022-09-19
申请人： Micron Technology, Inc.
发明人： Yi Fang Lee , Jaydip Guha , Lars P. Heineck , Kamal M. Karda , Si-Woo Lee , Terrence B. McDaniel , Scott E. Sills , Kevin J. Torek , Sheng-Wei Yang
IPC分类号： H01L27/12 , H01L21/84
摘要： An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

10. 发明授权

US11488981B2 Array of vertical transistors and method used in forming an array of vertical transistors 有权
公开(公告)号：US11488981B2
公开(公告)日：2022-11-01
申请号：US16934607
申请日：2020-07-21
申请人： Micron Technology, Inc.
发明人： Yi Fang Lee , Jaydip Guha , Lars P. Heineck , Kamal M. Karda , Si-Woo Lee , Terrence B. McDaniel , Scott E. Sills , Kevin J. Torek , Sheng-Wei Yang
IPC分类号： H01L27/12 , H01L21/84 , H01L27/13
摘要： An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

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