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1. 发明申请

US20130215699A1 MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD 有权
标题翻译：存储器银行信号耦合缓冲器和方法
公开(公告)号：US20130215699A1
公开(公告)日：2013-08-22
申请号：US13846452
申请日：2013-03-18
申请人： Micron Technology, Inc.
发明人： Aidan Shori , Sumit Chopra
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1048 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/4094 , G11C11/4096 , G11C11/4097
摘要： A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.
摘要翻译：存储器阵列包含通过多个数据线彼此耦合的多个存储体。每个数据线被分成阵列内的多个段。相应的双向缓冲器将读数据从第一方向上的一个段耦合到另一个段，并且将数据从一个段耦合到与第一方向相反的第二方向的另一方。数据线可以是将不同存储单元组彼此耦合的本地数据读/写线和相应的数据端，将相应列中的存储单元耦合到相应的读出放大器的数字线，激活存储单元中的存储单元的字线相应的行或阵列内的其他一些信号线。存储器阵列还包括用于将各个数据线的段预充电为预充电电压的预充电电路。

2. 发明授权

US10789998B2 Memory bank signal coupling buffer and method 有权
公开(公告)号：US10789998B2
公开(公告)日：2020-09-29
申请号：US16051281
申请日：2018-07-31
申请人： MICRON TECHNOLOGY, INC.
发明人： Aidan Shori , Sumit Chopra
IPC分类号： G11C7/12 , G11C8/06 , G11C8/08 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C7/10 , G11C7/22 , G11C8/10
摘要： A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

3. 发明申请

US20180336939A1 MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD 审中-公开
公开(公告)号：US20180336939A1
公开(公告)日：2018-11-22
申请号：US16051281
申请日：2018-07-31
申请人： MICRON TECHNOLOGY, INC.
发明人： Aidan Shori , Sumit Chopra
IPC分类号： G11C7/12 , G11C11/4097 , G11C11/4096 , G11C11/4094 , G11C8/10 , G11C7/10 , G11C8/06 , G11C7/22 , G11C8/08
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1048 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/4094 , G11C11/4096 , G11C11/4097
摘要： A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

4. 发明申请

US20170125075A1 MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD 审中-公开
公开(公告)号：US20170125075A1
公开(公告)日：2017-05-04
申请号：US15405839
申请日：2017-01-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Aidan Shori , Sumit Chopra
IPC分类号： G11C7/12 , G11C8/10 , G11C7/10 , G11C7/22
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1048 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/4094 , G11C11/4096 , G11C11/4097
摘要： A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

5. 发明授权

US09601168B2 Memory bank signal coupling buffer and method 有权
公开(公告)号：US09601168B2
公开(公告)日：2017-03-21
申请号：US13846452
申请日：2013-03-18
申请人： Micron Technology, Inc.
发明人： Aidan Shori , Sumit Chopra
IPC分类号： G11C7/10 , G11C8/06 , G11C8/08 , G11C11/4094 , G11C11/4096 , G11C11/4097
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1048 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/4094 , G11C11/4096 , G11C11/4097
摘要： A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

6. 发明授权

US10121523B2 Memory bank signal coupling buffer and method 有权
公开(公告)号：US10121523B2
公开(公告)日：2018-11-06
申请号：US15405839
申请日：2017-01-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Aidan Shori , Sumit Chopra
IPC分类号： G11C7/12 , G11C8/06 , G11C8/08 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C7/10 , G11C7/22 , G11C8/10
摘要： A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

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