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1. 发明授权

US08233329B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

2. 发明授权

US08638624B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08638624B2
公开(公告)日：2014-01-28
申请号：US13561248
申请日：2012-07-30
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

3. 发明申请

US20120287726A1 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
标题翻译：用于存储器编程的架构和方法
公开(公告)号：US20120287726A1
公开(公告)日：2012-11-15
申请号：US13561248
申请日：2012-07-30
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

4. 发明申请

US20100091582A1 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
标题翻译：用于存储器编程的架构和方法
公开(公告)号：US20100091582A1
公开(公告)日：2010-04-15
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

5. 发明授权

US07639534B2 Device, system, and method of bit line selection of a flash memory 有权
标题翻译： Flash存储器的位线选择的设备，系统和方法
公开(公告)号：US07639534B2
公开(公告)日：2009-12-29
申请号：US11860949
申请日：2007-09-25
申请人： Michele Incarnati , Giovanni Santin , Violante Moschiano , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Violante Moschiano , Tommaso Vali
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state.
摘要翻译： Flash存储器的位线选择的设备，系统和方法。在一些说明性实施例中，当位线处于未选择状态时，该方法可以包括沿闪速存储器的至少一个位线的至少一个位置连接到地，其中位线连接到多路复用器，并且其中至少一个存储器扇区耦合到多路复用器和位置之间的位线; 以及当所述位线处于选定状态时将所述位置连接到预充电路径。

6. 发明申请

US20090080253A1 DEVICE, SYSTEM, AND METHOD OF BIT LINE SELECTION OF A FLASH MEMORY 有权
标题翻译：闪存存储器的位线选择的设备，系统和方法
公开(公告)号：US20090080253A1
公开(公告)日：2009-03-26
申请号：US11860949
申请日：2007-09-25
申请人： MICHELE INCARNATI , Giovanni Santin , Violante Moschiano , Tommaso Vali
发明人： MICHELE INCARNATI , Giovanni Santin , Violante Moschiano , Tommaso Vali
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state. Other embodiments are described and claimed.
摘要翻译： Flash存储器的位线选择的设备，系统和方法。在一些说明性实施例中，当位线处于未选择状态时，该方法可以包括沿闪速存储器的至少一个位线的至少一个位置连接到地，其中位线连接到多路复用器，并且其中至少一个存储器扇区耦合到多路复用器和位置之间的位线; 以及当所述位线处于选定状态时将所述位置连接到预充电路径。描述和要求保护其他实施例。

7. 发明授权

US08395939B2 Compensation of back pattern effect in a memory device 有权
标题翻译：在存储器件中补偿背面图案效果
公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
申请人： Tommaso Vali , Violante Moschiano , Giovanni Santin
发明人： Tommaso Vali , Violante Moschiano , Giovanni Santin
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译：在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。通过偏置字线的读取操作产生位线电流。作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。这种背面图案效果指示用于随后的读取操作以调整操作的时间。

8. 发明授权

US08593876B2 Sensing scheme in a memory device 有权
标题翻译：存储设备中的感应方案
公开(公告)号：US08593876B2
公开(公告)日：2013-11-26
申请号：US13085611
申请日：2011-04-13
申请人： Violante Moschiano , Giovanni Santin , Tommaso Vali
发明人： Violante Moschiano , Giovanni Santin , Tommaso Vali
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C16/26
摘要： Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
摘要翻译：公开了在存储器件中操作存储器件，产生存储器件中的参考电流以及感测存储器单元的数据状态的方法。一种这样的方法包括产生在读出放大器电路中使用的参考电流，以在存储器件内进行感测操作的同时管理泄漏电流。另一种这样的方法激活两个串联耦合晶体管中的一个，同时激活和去激活与第一晶体管串联耦合的第二晶体管，从而调节通过两个串联耦合的晶体管的电流并建立特定的参考电流。

9. 发明授权

US08553461B2 Method for kink compensation in a memory 有权
公开(公告)号：US08553461B2
公开(公告)日：2013-10-08
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

10. 发明授权

US08243521B2 Method for kink compensation in a memory 有权
标题翻译：存储器中的扭结补偿方法
公开(公告)号：US08243521B2
公开(公告)日：2012-08-14
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

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