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1. 发明公开

US20240338327A1 DEVICES, METHODS, AND SYSTEMS FOR DISAGGREGATED MEMORY RESOURCES IN A COMPUTING ENVIRONMENT 审中-公开
公开(公告)号：US20240338327A1
公开(公告)日：2024-10-10
申请号：US18747156
申请日：2024-06-18
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Dimitrios Syrivelis , Paraskevas Bakopoulos , Ioannis (Giannis) Patronas , Elad Mentovich , James Stephen Fields , Haggai Eran , Liran Liss
IPC分类号： G06F13/16
CPC分类号： G06F13/1642
摘要： A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.

2. 发明申请

US20230099304A1 Zero-copy processing 有权
公开(公告)号：US20230099304A1
公开(公告)日：2023-03-30
申请号：US17488362
申请日：2021-09-29
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Haggai Eran , Liran Liss , Yuval Shpigelman , Idan Burstein
IPC分类号： G06F3/06
摘要： In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

3. 发明授权

US11184439B2 Communication with accelerator via RDMA-based network adapter 有权
公开(公告)号：US11184439B2
公开(公告)日：2021-11-23
申请号：US16827912
申请日：2020-03-24
申请人： Mellanox Technologies, Ltd.
发明人： Haggai Eran , Dotan David Levi , Maxim Fudim , Liran Liss
IPC分类号： H04L29/08 , G06F13/28 , G06F15/173
摘要： A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

4. 发明授权

US12045178B2 Devices, methods, and systems for disaggregated memory resources in a computing environment 有权
公开(公告)号：US12045178B2
公开(公告)日：2024-07-23
申请号：US17673105
申请日：2022-02-16
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Dimitrios Syrivelis , Paraskevas Bakopoulos , Ioannis (Giannis) Patronas , Elad Mentovich , James Stephen Fields, Jr. , Haggai Eran , Liran Liss
IPC分类号： G06F13/16
CPC分类号： G06F13/1642
摘要： A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.

5. 发明申请

US20210203610A1 Computational accelerator for packet payload operations 有权
公开(公告)号：US20210203610A1
公开(公告)日：2021-07-01
申请号：US17204968
申请日：2021-03-18
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Boris Pismenny , Liran Liss , Ilya Lesokhin , Haggai Eran , Adi Menachem
IPC分类号： H04L12/833 , H04L29/06 , H04L12/931 , H04L29/08 , H04L12/851 , H04L12/413 , H04L12/00
摘要： Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.

6. 发明授权

US10841243B2 NIC with programmable pipeline 有权
公开(公告)号：US10841243B2
公开(公告)日：2020-11-17
申请号：US16012826
申请日：2018-06-20
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Dotan Levi , Liran Liss , Haggai Eran , Noam Bloch , Idan Burstein , Lior Narkis , Avraham Ganor
IPC分类号： H04L12/933 , G06F13/40 , G06F9/455 , H04L12/861 , H04L29/08
CPC分类号： H04L49/1546 , G06F9/45558 , G06F13/4068 , H04L49/9068 , H04L67/10 , G06F2009/45595
摘要： A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

7. 发明申请

US20140089451A1 Application-assisted handling of page faults in I/O operations 有权
标题翻译： I / O操作中页面故障的应用辅助处理
公开(公告)号：US20140089451A1
公开(公告)日：2014-03-27
申请号：US13628155
申请日：2012-09-27
申请人： MELLANOX TECHNOLOGIES LTD.
发明人： Haggai Eran , Shachar Raindel , Liran Liss , Noam Bloch
IPC分类号： G06F15/167
CPC分类号： G06F12/08 , G06F12/1081
摘要： A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.
摘要翻译：一种用于数据传输的方法包括在主计算机的操作系统中接收由主机处理器上运行的用户应用程序发起的指令，该指令标识主计算机的虚拟存储器的页面，该页面将用于在消息中接收数据通过网络传送到主计算机，但尚未被主计算机接收。响应该指令，页面被加载到存储器中，并且在接收到消息时，数据被写入加载的页面。

8. 发明申请

US20140089450A1 Look-Ahead Handling of Page Faults in I/O Operations 有权
标题翻译：在I / O操作中预先处理页面错误
公开(公告)号：US20140089450A1
公开(公告)日：2014-03-27
申请号：US13628075
申请日：2012-09-27
申请人： MELLANOX TECHNOLOGIES LTD.
发明人： Shachar Raindel , Haggai Eran , Liran Liss , Noam Bloch
IPC分类号： G06F12/00 , G06F15/167
CPC分类号： G06F3/067 , G06F3/061 , G06F3/0656 , G06F3/0659
摘要： A method for data transfer includes receiving in an input/output (I/O) operation a first segment of data to be written to a specified virtual address in a host memory. Upon receiving the first segment of the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. At least one second page of the host memory is identified, to which a second segment of the data is expected to be written. Responsively to detecting that the first page is swapped out and to identifying the at least one second page, at least the first and second pages are swapped into the host memory. After swapping at least the first and second pages into the host memory, the data are written to the first and second pages.
摘要翻译：一种用于数据传输的方法包括在输入/输出（I / O）操作中接收要写入主机存储器中的指定虚拟地址的第一数据段。在接收到数据的第一段时，检测到包含指定虚拟地址的第一页被转换出主机存储器。标识主机存储器的至少一个第二页，期望数据的第二段被写入到其上。响应于检测到第一页面被换出并且识别至少一个第二页面，至少第一页面和第二页面被交换到主机存储器中。至少将第一页和第二页交换到主机存储器之后，数据被写入第一页和第二页。

9. 发明授权

US11693804B2 Cross bus memory mapping 有权
公开(公告)号：US11693804B2
公开(公告)日：2023-07-04
申请号：US17338131
申请日：2021-06-03
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Alex Rosenbaum , Oren Duer , Alexander Mikheev , Nitzan Carmi , Haggai Eran
IPC分类号： G06F13/00 , G06F13/40 , G06F15/173 , G06F13/16 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/1673 , G06F13/4221 , G06F15/17331
摘要： A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.

10. 发明申请

US20200314181A1 Communication with accelerator via RDMA-based network adapter 审中-公开
公开(公告)号：US20200314181A1
公开(公告)日：2020-10-01
申请号：US16827912
申请日：2020-03-24
申请人： Mellanox Technologies, Ltd.
发明人： Haggai Eran , Dotan David Levi , Maxim Fudim , Liran Liss
IPC分类号： H04L29/08
摘要： A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

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