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1. 发明公开

US20240137130A1 CIRCUIT FOR MULTI-PATH INTERFERENCE MITIGATION IN AN OPTICAL COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20240137130A1
公开(公告)日：2024-04-25
申请号：US18393017
申请日：2023-12-21
申请人： MARVELL ASIA PTE LTD
发明人： Benjamin P. SMITH , Jamal RIANI , Sudeep BHOJA , Arash FARHOODFAR , Vipul BHATT
IPC分类号： H04B10/58 , H04B10/00 , H04B10/2507 , H04B10/516 , H04B10/54 , H04B10/69
CPC分类号： H04B10/58 , H04B10/00 , H04B10/2507 , H04B10/25073 , H04B10/5161 , H04B10/541 , H04B10/697 , H04B10/6971
摘要： An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.

2. 发明公开

US20240223924A1 NETWORKING SWITCHING DEVICES AND METHODS THEREOF 审中-公开
公开(公告)号：US20240223924A1
公开(公告)日：2024-07-04
申请号：US18439295
申请日：2024-02-12
申请人： MARVELL ASIA PTE LTD
发明人： Whay Sing LEE , Arash FARHOODFAR , Volodymyr SHVYDUN , Michael DUCKERING
IPC分类号： H04Q11/00 , H04B10/516 , H04J14/02 , H04L1/00
CPC分类号： H04Q11/0062 , H04B10/516 , H04J14/02 , H04L1/0003 , H04L1/0045 , H04L1/0061 , H04Q11/0005 , H04Q2011/0016 , H04Q2011/002 , H04Q2011/0088 , H04Q2201/02
摘要： A communication device includes a plurality of communication pipelines configured to receive respective input data streams and a multiplexer coupled to the plurality of communication pipelines. The multiplexer is configured to generate an output data stream by combining the input data streams and to insert one or more special characters into the output data stream in response to a fault with one of the communication pipelines.

3. 发明公开

US20240171306A1 METHODS AND SYSTEMS FOR DATA TRANSMISSION 审中-公开
公开(公告)号：US20240171306A1
公开(公告)日：2024-05-23
申请号：US18421304
申请日：2024-01-24
申请人： MARVELL ASIA PTE LTD
发明人： Benjamin SMITH , Jamal RIANI , Arash FARHOODFAR , Sudeep BHOJA
IPC分类号： H04L1/00 , H03M13/19 , H03M13/25 , H03M13/29
CPC分类号： H04L1/0057 , H03M13/19 , H03M13/251 , H03M13/2906 , H04L1/0041 , H04L1/0059 , H04L1/0064 , H04L1/0071 , H04L1/0643
摘要： An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.

4. 发明公开

US20240063940A1 SOFT FEC WITH PARITY CHECK 审中-公开
公开(公告)号：US20240063940A1
公开(公告)日：2024-02-22
申请号：US18384267
申请日：2023-10-26
申请人： Marvell Asia Pte Ltd
发明人： Jamal RIANI , Benjamin SMITH , Volodymyr SHVYDUN , Sudeep BHOJA , Arash FARHOODFAR
IPC分类号： H04L1/00 , H03M13/15 , H03M13/29 , H04B14/02
CPC分类号： H04L1/0041 , H03M13/1515 , H03M13/2906 , H04B14/023 , H04L1/0058
摘要： A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.

5. 发明申请

US20220224997A1 NETWORKING SWITCHING DEVICES AND METHODS THEREOF 有权
公开(公告)号：US20220224997A1
公开(公告)日：2022-07-14
申请号：US17684815
申请日：2022-03-02
申请人： MARVELL ASIA PTE LTD.
发明人： Whay Sing LEE , Arash FARHOODFAR , Volodymyr SHVYDUN , Michael DUCKERING
IPC分类号： H04Q11/00 , H04L1/00 , H04J14/02 , H04B10/516
摘要： A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.

6. 发明申请

US20220201225A1 SOFT FEC WITH PARITY CHECK 有权
公开(公告)号：US20220201225A1
公开(公告)日：2022-06-23
申请号：US17693931
申请日：2022-03-14
申请人： Marvell Asia Pte Ltd.
发明人： Jamal RIANI , Benjamin SMITH , Volodymyr SHVYDUN , Sudeep BHOJA , Arash FARHOODFAR
IPC分类号： H04N5/28 , G06F3/0481 , G06F3/16 , G10L15/22 , H04R1/08 , H04N5/225 , H04R1/02 , H04N5/232 , G06F3/14
摘要： A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.

7. 发明公开

US20240118819A1 MEMORY ALLOCATION AND REALLOCATION FOR PROGRAM INSTRUCTIONS AND DATA USING INTERMEDIATE PROCESSOR 审中-公开
公开(公告)号：US20240118819A1
公开(公告)日：2024-04-11
申请号：US18544745
申请日：2023-12-19
申请人： Marvell Asia Pte Ltd
发明人： Arash FARHOODFAR , Whay Sing Lee
IPC分类号： G06F3/06
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0673
摘要： Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.

8. 发明申请

US20220326864A1 RAM BLOCK ALLOCATOR 有权
公开(公告)号：US20220326864A1
公开(公告)日：2022-10-13
申请号：US17225789
申请日：2021-04-08
申请人： Marvell Asia Pte, Ltd.
发明人： Arash FARHOODFAR , Whay LEE
IPC分类号： G06F3/06
摘要： Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.

9. 发明申请

US20220173833A1 SOFT FEC WITH PARITY CHECK 有权
公开(公告)号：US20220173833A1
公开(公告)日：2022-06-02
申请号：US17677481
申请日：2022-02-22
申请人： Marvell Asia Pte Ltd.
发明人： Jamal RIANI , Benjamin SMITH , Volodymyr SHVYDUN , Srinivas SWAMINATHAN , Arash FARHOODFAR
IPC分类号： H04L1/00
摘要： A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

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