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1. 发明授权

US10644018B2 3D memory having plural lower select gates 有权
公开(公告)号：US10644018B2
公开(公告)日：2020-05-05
申请号：US15951776
申请日：2018-04-12
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chih-Wei Lee , Cheng-Hsien Cheng , Shaw-Hung Ku , Atsuhiro Suzuki
IPC分类号： H01L27/1157 , G11C16/08 , G11C16/04 , H01L27/11582
CPC分类号： H01L27/1157 , G11C16/0483 , G11C16/08 , H01L27/11582
摘要： A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.

2. 发明申请

US20160372202A1 NON-VOLATILE MEMORY DEVICE HAVING MULTIPLE STRING SELECT LINES 有权
标题翻译：具有多条选择线的非易失性存储器件
公开(公告)号：US20160372202A1
公开(公告)日：2016-12-22
申请号：US14742054
申请日：2015-06-17
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Atsuhiro Suzuki , Chih-Wei Lee , Shaw-Hung Ku
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3427
摘要： Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.
摘要翻译：本文中设想的方法和装置用于增强非易失性存储器件的程序性能。在示例实施例中，非易失性存储器件包括包括多个层的非易失性存储器单元的3D阵列，每个层包括非易失性存储器单元的NAND串，耦合到位线的NAND串和多个SSL和字线，所述SSL和所述字线与所述NAND串正交排列，所述字线在所述多个NAND串的表面和所述字线之间的交叉点处建立所述非易失性存储单元，所述NAND串中的每一个还包括多个SSL晶体管将SSL耦合到NAND串，其中至少第一SSL被配置为接收第一电压，第二SSL被配置为在第二电压下接收，并且其中第二SSL更靠近字线。

3. 发明授权

US10460797B2 Method for programming non-volatile memory and memory system 有权
公开(公告)号：US10460797B2
公开(公告)日：2019-10-29
申请号：US15698812
申请日：2017-09-08
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shaw-Hung Ku , Ta-Wei Lin , Cheng-Hsien Cheng , Chih-Wei Lee , Wen-Jer Tsai
IPC分类号： G11C16/04 , G11C11/56 , G11C16/34
摘要： A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

4. 发明申请

US20170098478A1 METHOD AND APPARATUS FOR IMPROVING YIELD FOR NON-VOLATILE MEMORY 审中-公开
公开(公告)号：US20170098478A1
公开(公告)日：2017-04-06
申请号：US14873486
申请日：2015-10-02
申请人： Macronix International Co., Ltd.
发明人： Chih-Wei Lee , Cheng-Hsien Cheng , Shaw-Hung Ku , Wen-Pin Lu
IPC分类号： G11C29/38 , G11C16/26 , G11C29/44 , G11C16/14
CPC分类号： G11C29/38 , G11C16/08 , G11C16/26 , G11C29/025 , G11C29/44 , G11C2029/1202
摘要： A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.

5. 发明授权

US09548121B2 Memory device having only the top poly cut 有权
标题翻译：仅具有顶部多边形切割的存储器件
公开(公告)号：US09548121B2
公开(公告)日：2017-01-17
申请号：US14742944
申请日：2015-06-18
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chih-Wei Lee , Shaw-Hung Ku , Cheng-Hsien Cheng
IPC分类号： G11C16/08 , G11C16/04 , H01L27/115 , H01L21/768
CPC分类号： G11C16/0483 , G11C2216/02 , H01L21/76802 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.
摘要翻译：本文中设想的方法和装置用于增强非易失性存储器件的效率。在示例实施例中，非易失性存储器件包括基板和非易失性存储单元的3D阵列，3D阵列包括通过绝缘层彼此分离的多个导电层，多个导电层包括顶层，顶部层包括n个字符串选择行（SSL）和一个或多个底层，顶层还包括n-1个切割，每个切割电隔离两个SSL，其中每个切割被切割到顶层的深度并且不延伸到底层和与多个层正交布置的多个垂直通道，多个通道中的每一个包括一串存储器单元，多个串中的每一个耦合到位线，SSL和一个或多个字线。

6. 发明授权

US09437612B1 Three-dimensional memory 有权
标题翻译：三维记忆
公开(公告)号：US09437612B1
公开(公告)日：2016-09-06
申请号：US14832220
申请日：2015-08-21
申请人： MACRONIX International Co., Ltd.
发明人： Chih-Wei Lee , Cheng-Hsien Cheng , Shaw-Hung Ku , Wen-Pin Lu
IPC分类号： H01L29/10 , H01L27/115 , H01L29/16 , H01L29/04 , H01L29/49 , H01L29/51 , H01L23/528 , H01L23/532 , H01L29/06
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L23/528 , H01L23/53271 , H01L27/11556 , H01L29/04 , H01L29/0649 , H01L29/16 , H01L29/4916 , H01L29/518 , H01L29/7889 , H01L29/7926
摘要： A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.
摘要翻译：三维存储器，其包括存储单元堆叠结构。存储单元堆叠结构由多个存储单元阵列结构和绝缘层交替堆叠，并且每个存储单元阵列结构包括字线，有源层，复合层和源极/漏极。字线，有源层和复合层沿Y方向延伸。有源层设置在相邻字线之间。复合层设置在相邻字线和相邻有源层之间，并且每个复合层从有源层依次包括第一介电层，电荷存储层和第二介质层。源/排水口以相等的间隔设置在活性层中。存储单元包括两个相邻的源/漏极，两个相邻源极/漏极之间的有源层，有源层上的第一介电层，电荷存储层和第二介电层以及字线。

7. 发明申请

US20170025179A1 NON-VOLATILE MEMORY DEVICE FOR REDUCING BIT LINE RECOVERY TIME 审中-公开
标题翻译：用于减少位线恢复时间的非易失性存储器件
公开(公告)号：US20170025179A1
公开(公告)日：2017-01-26
申请号：US14808745
申请日：2015-07-24
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Atsuhiro Suzuki , Chih-Wei Lee , Shaw-Hung Ku
IPC分类号： G11C16/24 , G11C16/04 , G11C16/10
CPC分类号： G11C16/24 , G11C16/0466 , G11C16/0483 , G11C16/10
摘要： Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.
摘要翻译：本文中设想的方法和装置用于减少非易失性存储器件的位线恢复时间。在示例性实施例中，非易失性存储器件包括非易失性存储器单元的3D阵列，包括多个块，每个块包括多个NAND串，每个NAND串耦合到位线和字线，与NAND串正交排列的字线和在NAND串和字线的表面之间的交叉点建立存储单元，以及位于3D阵列边缘的第一组放电晶体管，耦合到相应的位线并且被配置为用于BL放电，以及第二组放电晶体管，其定位成使得BL电位的第一部分通过第一组放电晶体管放电，并且通过第二组放电第二部分。

8. 发明授权

US10340017B2 Erase-verify method for three-dimensional memories and memory system 有权
公开(公告)号：US10340017B2
公开(公告)日：2019-07-02
申请号：US15803986
申请日：2017-11-06
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shaw-Hung Ku , Yu-Hung Huang , Cheng-Hsien Cheng , Chih-Wei Lee , Atsuhiro Suzuki , Wen-Jer Tsai
IPC分类号： G11C11/34 , G11C16/34 , G11C16/16 , G11C8/14
摘要： An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

9. 发明授权

US09524784B1 Device and method for improved threshold voltage distribution for non-volatile memory 有权
标题翻译：用于改善非易失性存储器阈值电压分布的装置和方法
公开(公告)号：US09524784B1
公开(公告)日：2016-12-20
申请号：US14848524
申请日：2015-09-09
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Cheng-Hsien Cheng , Chih-Wei Lee , Shaw-Hung Ku , Wen-Pin Lu
IPC分类号： G11C16/10 , G11C16/14 , G11C16/26 , G11C16/04 , H01L27/115
CPC分类号： H01L27/11578 , G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582
摘要： The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.
摘要翻译：本发明提供了用于控制对应于在非易失性存储器件的单元上执行功能的电压阈值分布的方法和相关联的器件。在一个实施例中，提供了一种方法。该方法可以包括提供非易失性存储器件。该设备包括一个或多个字符串，每个字符串包括多个单元，多个单元包括第一单元和第二单元。该方法还包括通过向第一单元施加第一功能电压和向第二单元施加第二功能电压来执行非易失性存储器件的功能。第一功能电压和第二功能电压不同。

10. 发明授权

US09437319B1 Method for programming non-volatile memory with reduced bit line interference and associated device 有权
标题翻译：用于减少位线干扰和相关设备的非易失性存储器编程方法
公开(公告)号：US09437319B1
公开(公告)日：2016-09-06
申请号：US14750065
申请日：2015-06-25
申请人： Macronix International Co., Ltd.
发明人： Atsuhiro Suzuki , Ya Jui Lee , Kuan Fu Chen , Chih-Wei Lee
IPC分类号： G11C11/34 , G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C16/3481 , G11C16/3486
摘要： Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.
摘要翻译：提供了在编程非易失性存储器时减少位线干扰的方法，装置和/或类似装置。一种方法包括提供包括一组单元的非易失性存储器件，每个单元与位线相关联; 拍摄每个单元格上的编程电压; 检测每个单元的阈值电压; 至少部分地基于每个单元的检测到的阈值电压来识别该组单元的快速子集和该组单元的慢子集; 并拍摄编程电压，直到每个单元的阈值电压大于验证电压。对于每个镜头，快速位线偏置被施加到与快速子集的每个单元相关联的位线，并且慢位线偏置被施加到与慢子集的每个单元相关联的位线。

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