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1. 发明授权

US07522169B1 Apparatus and method for selective attribute distribution to parallel processors 有权
标题翻译：用于选择属性分配到并行处理器的装置和方法
公开(公告)号：US07522169B1
公开(公告)日：2009-04-21
申请号：US11300228
申请日：2005-12-13
申请人： Lukito Muliadi , Justin S. Legakis
发明人： Lukito Muliadi , Justin S. Legakis
IPC分类号： G06T1/20 , G06F15/16 , G06F15/80 , G06F9/46
CPC分类号： G06F15/16 , G06F9/5066 , G06T1/20
摘要： A graphics processing unit has a set of parallel processing units. A primitive pipeline delivers tiles of a primitive to selected processing units of the set of processing units. An attribute pipeline distributes attributes to the selected processing units when the end of the primitive is reached, while withholding attributes from the remaining processing units of the set of processing units.
摘要翻译：图形处理单元具有一组并行处理单元。原始流水线将原始图块传送到该组处理单元的选定处理单元。当到达原语的结尾时，属性管道将属性分配给所选择的处理单元，同时从该组处理单元的其余处理单元中扣留属性。

2. 发明授权

US08059128B1 Apparatus and method for performing blit operations across parallel processors 有权
标题翻译：在并行处理器上执行blit操作的装置和方法
公开(公告)号：US08059128B1
公开(公告)日：2011-11-15
申请号：US11407464
申请日：2006-04-19
申请人： Justin S. Legakis , Mark J. French , Steven E. Molnar , Lukito Muliadi
发明人： Justin S. Legakis , Mark J. French , Steven E. Molnar , Lukito Muliadi
IPC分类号： G06F15/80 , G06F21/00
CPC分类号： G09G5/363 , G09G2352/00 , G09G2360/127
摘要： A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.
摘要翻译：在并行处理系统中执行blit操作的方法包括将blit操作划分成多个像素，以任何顺序执行与第一批次相关联的像素的读取，确认与第一批相关联的所有像素读取完成，以及以任何顺序执行与第一批相关联的像素的写入。第一批的像素和附加批次的像素被应用于并行处理器，其中并行处理器包括通过分布在并行处理器上的入口点和出口点定义的畜栏。

3. 发明授权

US08667200B1 Fast and highly scalable quota-based weighted arbitration 有权
标题翻译：快速且高度可扩展的配额加权仲裁
公开(公告)号：US08667200B1
公开(公告)日：2014-03-04
申请号：US12712109
申请日：2010-02-24
申请人： Lukito Muliadi , Raymond Hoi Man Wong , Madhukiran V. Swarna , Samuel H. Duncan
发明人： Lukito Muliadi , Raymond Hoi Man Wong , Madhukiran V. Swarna , Samuel H. Duncan
IPC分类号： G06F12/00 , H04L12/28
CPC分类号： G06F13/364 , H04L47/623 , H04L47/821
摘要： One embodiment of the present invention sets forth a technique for arbitrating between a set of requesters that transmit data transmission requests to the weighted LRU arbiter. Each data transmission request is associated with a specific amount of data to be transmitted over the crossbar unit. Based on the priority state associated with each requester, the weighted LRU arbiter then selects the requester in the set of requesters with the highest priority. The weighted LRU arbiter then decrements the weight associated with the selected requester stored in a corresponding weight store based on the size of the data to be transmitted. If the decremented weight is equal to or less than zero, then the priority associated with the selected requester is set to a lowest priority. If, however, the decremented weight is greater than zero, then the priority associated with the selected requester is not changed.
摘要翻译：本发明的一个实施例提出了一种用于在向加权的LRU仲裁器发送数据传输请求的请求者组之间进行仲裁的技术。每个数据传输请求与通过交叉开关单元传输的特定数据量相关联。基于与每个请求者相关联的优先级状态，加权LRU仲裁器然后选择具有最高优先级的请求者组中的请求者。然后，加权的LRU仲裁器基于要发送的数据的大小来减去与存储在对应权重存储器中的所选择的请求者相关联的权重。如果递减权重等于或小于零，则与所选择的请求者相关联的优先级被设置为最低优先级。然而，如果递减的权重大于零，则与所选请求者相关联的优先级不改变。

4. 发明授权

US08683089B1 Method and apparatus for equalizing a bandwidth impedance mismatch between a client and an interface 有权
标题翻译：用于均衡客户端和接口之间的带宽阻抗不匹配的方法和装置
公开(公告)号：US08683089B1
公开(公告)日：2014-03-25
申请号：US12650371
申请日：2009-12-30
申请人： Raymond Hoi Man Wong , Samuel H. Duncan , Lukito Muliadi
发明人： Raymond Hoi Man Wong , Samuel H. Duncan , Lukito Muliadi
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/1642 , G06F9/3851 , G06F2213/0026
摘要： One or more client engines issues write transactions to system memory or peer parallel processor (PP) memory across a peripheral component interconnect express (PCIe) interface. The client engines may issue write transactions faster than the PCIe interface can transport those transactions, causing write transactions to accumulate within the PCIe interface. To prevent the accumulation of write transactions within the PCIe interface, an arbiter throttles write transactions received from the client engines based on the number of write transactions currently being transported across the PCIe interface.
摘要翻译：一个或多个客户端引擎通过外围组件互连快速（PCIe）接口向系统内存或对等并行处理器（PP）存储器发出写入事务。客户端引擎可能比PCIe接口可以传输这些事务更快地发出写事务，导致写事务在PCIe接口内累积。为了防止PCIe接口内写入事务的累积，仲裁器基于当前正在PCIe接口上传输的写入事务的数量来限制从客户机引擎接收的写入事务。

5. 发明授权

US08279231B1 Bandwidth impedance matching and starvation avoidance by read completion buffer allocation 有权
标题翻译：带宽阻抗匹配和通过读取完成缓冲区分配避免饥饿
公开(公告)号：US08279231B1
公开(公告)日：2012-10-02
申请号：US12260985
申请日：2008-10-29
申请人： Samuel Hammond Duncan , John H. Edmondson , Raymond Hoi Man Wong , Lukito Muliadi
发明人： Samuel Hammond Duncan , John H. Edmondson , Raymond Hoi Man Wong , Lukito Muliadi
IPC分类号： G06F12/02
CPC分类号： G06F12/1081
摘要： Read completion buffer space is allocated in accordance with a preset limit. When a read request is received from a client, the sum of a current allocation of the read completion buffer space and a new allocation of the read completion buffer space required by the read request is compared with the preset limit. If the preset limit is not exceeded, read completion buffer space is allocated to the read request. If the preset limit is exceeded, the read request is suspended until sufficient data is read out from the read completion buffer.
摘要翻译：读取完成缓冲区空间按照预设限制进行分配。当从客户端接收到读取请求时，读取完成缓冲区空间的当前分配和读取请求所需的读取完成缓冲区空间的新分配与预设限制进行比较。如果未超过预设限制，则读取完成缓冲区空间被分配给读请求。如果超出预设限制，读取请求将被暂停，直到从读取完成缓冲区读出足够的数据。

6. 发明授权

US08656117B1 Read completion data management 有权
标题翻译：读取完成数据管理
公开(公告)号：US08656117B1
公开(公告)日：2014-02-18
申请号：US12262141
申请日：2008-10-30
申请人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
发明人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
IPC分类号： G06F12/00
CPC分类号： G06F9/3836 , G06F9/3824
摘要： An input/output unit for a computer system that is interfaced with a memory unit having a plurality of partitions manages completions of read requests in the order that they were made. A read request buffer tracks the order in which the read requests were made so that read data responsive to the read requests can be completed and returned to a requesting client in the order the read requests were made.
摘要翻译：用于与具有多个分区的存储器单元连接的计算机系统的输入/输出单元按照它们的顺序管理读取请求的完成。读取请求缓冲器跟踪读取请求的顺序，使得响应于读取请求的读取数据可以被完成，并且以读取请求的顺序返回给请求客户端。

7. 发明授权

US08396993B2 Data packer for packing and aligning write data 有权
公开(公告)号：US08396993B2
公开(公告)日：2013-03-12
申请号：US13397591
申请日：2012-02-15
申请人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
发明人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F5/00 , G06F5/01
摘要： A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

8. 发明申请

US20120139928A1 DATA PACKER FOR PACKING AND ALIGNING WRITE DATA 有权
公开(公告)号：US20120139928A1
公开(公告)日：2012-06-07
申请号：US13397591
申请日：2012-02-15
申请人： Raymond Hoi Man WONG , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
发明人： Raymond Hoi Man WONG , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
IPC分类号： G06F13/14 , G06F12/10 , G06F5/00
CPC分类号： G06F5/00 , G06F5/01
摘要： A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

9. 发明授权

US08380896B2 Data packer for packing and aligning write data 有权
公开(公告)号：US08380896B2
公开(公告)日：2013-02-19
申请号：US13397586
申请日：2012-02-15
申请人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
发明人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F5/00 , G06F5/01
摘要： A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

10. 发明授权

US08380895B2 Data packer for packing and aligning write data 有权
标题翻译：用于打包和对齐写入数据的数据打包器
公开(公告)号：US08380895B2
公开(公告)日：2013-02-19
申请号：US13397583
申请日：2012-02-15
申请人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
发明人： Raymond Hoi Man Wong , Samuel Hammond Duncan , Lukito Muliadi , Madhukiran V. Swarna
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F5/00 , G06F5/01
摘要： A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.
摘要翻译：计算机系统的输入/输出集线器的数据封装器在将写入数据写入计算机系统的存储器单元之前对其提供的写入数据进行打包和格式化。更具体地，数据打包器累积从较低带宽客户端接收的写入数据，以便传送到高带宽存储器接口。此外，数据封装器对准写入数据，使得当从写入数据封装器读出写入数据时，不需要进一步的对准。

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