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1. 发明授权

US06200913B1 Cure process for manufacture of low dielectric constant interlevel dielectric layers 有权
标题翻译：用于制造低介电常数层间电介质层的固化工艺
公开(公告)号：US06200913B1
公开(公告)日：2001-03-13
申请号：US09191040
申请日：1998-11-12
申请人： Lu You , Simon S. Chan , John Iacoponi , Richard J. Huang , Robin Cheung
发明人： Lu You , Simon S. Chan , John Iacoponi , Richard J. Huang , Robin Cheung
IPC分类号： H01L21324
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/31058 , H01L21/3124
摘要： This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.
摘要翻译：本发明包括改进旋涂电介质层固化的方式。半导体晶片被涂覆有用于旋涂电介质材料的前体，并且在溶液变薄并均匀之后，将晶片放置在固化炉中，任选地包含惰性气体，并预热到低于该温度的温度在半导体晶片中不产生热机械应力和/或氧化。然后将固化炉内的温度升高至固化温度，然后缓慢降低温度，以防止形成应力裂纹和薄膜的介电功能的损失。本发明的固化方法可用于制造采用各种旋涂材料的半导体器件。

2. 发明授权

US6093635A High integrity borderless vias with HSQ gap filled patterned conductive layers 失效
标题翻译：高完整性无边界通孔与HSQ间隙填充图案导电层
公开(公告)号：US6093635A
公开(公告)日：2000-07-25
申请号：US993124
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
发明人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

3. 发明授权

US5861677A Low RC interconnection 失效
标题翻译：低RC互连
公开(公告)号：US5861677A
公开(公告)日：1999-01-19
申请号：US890905
申请日：1997-07-10
申请人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/768 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/532 , B29B13/00 , B05D3/02 , H01L21/283
CPC分类号： H01L23/3142 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044
摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.
摘要翻译：低阻抗延迟互连图案由诸如铜的低电阻率金属和诸如有机聚合物的低介电常数材料形成。在使用粘合促进剂的低电阻率金属和低介电常数材料之间形成中间粘合层，例如硅烷类粘合促进剂。粘合促进剂可以施加在金属和电介质层之间或并入电介质层中。

4. 发明授权

US5760480A Low RC interconnection 失效
公开(公告)号：US5760480A
公开(公告)日：1998-06-02
申请号：US530658
申请日：1995-09-20
申请人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/768 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/532 , B29B13/00 , B05D3/02 , H01L21/283
CPC分类号： H01L23/3142 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044
摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.

5. 发明授权

US5670828A Tunneling technology for reducing intra-conductive layer capacitance 失效
标题翻译：用于降低导电层电容的隧道技术
公开(公告)号：US5670828A
公开(公告)日：1997-09-23
申请号：US391692
申请日：1995-02-21
申请人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： The control speed of semiconductor circuitry is increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.
摘要翻译：通过在导电图案的布线间隙中形成空气隧道以减少导电层电容来增加半导体电路的控制速度。

6. 发明授权

US5843836A Tunneling technology for reducing intra-conductive layer capacitance 失效
标题翻译：用于降低导电层电容的隧道技术
公开(公告)号：US5843836A
公开(公告)日：1998-12-01
申请号：US744655
申请日：1996-11-06
申请人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/441
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： The control speed of semiconductor circuitry is increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.
摘要翻译：通过在导电图案的布线间隙中形成空气隧道以减少导电层电容来增加半导体电路的控制速度。

7. 发明授权

US5635423A Simplified dual damascene process for multi-level metallization and interconnection structure 失效
标题翻译：用于多层次金属化和互连结构的简化双镶嵌工艺
公开(公告)号：US5635423A
公开(公告)日：1997-06-03
申请号：US320516
申请日：1994-10-11
申请人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
发明人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7681 , H01L21/76807 , H01L21/76813
摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
摘要翻译：通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。沟槽和通孔然后同时填充导电材料。

8. 发明授权

US6124201A Method for manufacturing semiconductors with self-aligning vias 失效
标题翻译：具有自对准通孔的半导体制造方法
公开(公告)号：US6124201A
公开(公告)日：2000-09-26
申请号：US097126
申请日：1998-06-12
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L21/60 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

9. 发明授权

US06400030B1 Self-aligning vias for semiconductors 有权
标题翻译：半导体自对准通孔
公开(公告)号：US06400030B1
公开(公告)日：2002-06-04
申请号：US09583817
申请日：2000-05-30
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

10. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

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