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    • 1. 发明授权
    • Method and circuit for DisplayPort video clock recovery
    • DisplayPort视频时钟恢复方法和电路
    • US08217689B2
    • 2012-07-10
    • US12675106
    • 2010-01-19
    • Lu YangSibing WangXiaoqian Zhang
    • Lu YangSibing WangXiaoqian Zhang
    • H03L7/06
    • H03L7/0807H03L7/16
    • A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.
    • 描述了一种用于恢复DisplayPort接收机的视频时钟的方法和电路。 本公开包括两个时钟分频器,直接数字合成(DDS),DisplayPort视频系统上的固定乘法器锁相环(PLL)。 DisplayPort接收器链路时钟被划分为较低频率作为DDS的输入,这可以降低DDS电路的性能要求。 来自时间戳值的输出间接地控制直接数字合成装置,然后驱动PLL以产生恢复时钟信号。 该技术适用于集成电路和现场可编程门阵列系统的实现。
    • 2. 发明申请
    • METHOD AND CIRCUIT FOR DISPLAYPORT VIDEO CLOCK RECOVERY
    • 显示视频时钟恢复的方法和电路
    • US20110267116A1
    • 2011-11-03
    • US12675106
    • 2010-01-19
    • Lu YangSibing WangXiaoqian Zhang
    • Lu YangSibing WangXiaoqian Zhang
    • H03L7/08
    • H03L7/0807H03L7/16
    • A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.
    • 描述了一种用于恢复DisplayPort接收机的视频时钟的方法和电路。 本公开包括两个时钟分频器,直接数字合成(DDS),DisplayPort视频系统上的固定乘法器锁相环(PLL)。 DisplayPort接收器链路时钟被划分为较低频率作为DDS的输入,这可以降低DDS电路的性能要求。 来自时间戳值的输出间接地控制直接数字合成装置,然后驱动PLL以产生恢复时钟信号。 该技术适用于集成电路和现场可编程门阵列系统的实现。
    • 9. 发明申请
    • SWITCHING FRAME AND ROUTER CLUSTER
    • 切换框架和路由器集群
    • US20100118867A1
    • 2010-05-13
    • US12691341
    • 2010-01-21
    • Dajun ZangLu YangWenhua DuDongcheng YangLingqiang FanGang GaiDa ZhouZhengjie Pu
    • Dajun ZangLu YangWenhua DuDongcheng YangLingqiang FanGang GaiDa ZhouZhengjie Pu
    • H04L12/50H04J14/00
    • H04L12/56H04L45/583H04L49/1515H04L49/45
    • A switching chassis includes more than one cascade unit and more than one switching unit, where: the cascade units have cascade interfaces to connect line processing chassis; the switching units have switching ports to connect the cascade interfaces; and any cascade interface of any cascade unit is connected to one switching port of any switching unit. A router cluster with the above switching chassis includes switching chassis and line processing chassis interconnected via optical fibers, where: any optical interface of any line processing chassis is connected to one cascade interface of any cascade unit; and any cascade interface of any cascade unit is connected to one switching port of any switching unit. With the present invention, the capacity of a router cluster can be expanded without the need to replace any component of the router cluster so that the expansion cost is lower.
    • 交换机箱包括多个级联单元和多个交换单元,其中:级联单元具有级联接口,用于连接线路处理机箱; 交换单元具有连接级联接口的交换端口; 并且任何级联单元的任何级联接口连接到任何交换单元的一个交换端口。 具有上述切换机架的路由器集群包括通过光纤互连的交换机箱和线路处理机箱,其中:任何线路处理机箱的任何光接口连接到任何级联单元的一个级联接口; 并且任何级联单元的任何级联接口连接到任何交换单元的一个交换端口。 利用本发明,可以扩展路由器集群的容量,而无需更换路由器集群的任何组件,从而扩展成本更低。
    • 10. 发明授权
    • Precursor formulation for battery active materials synthesis
    • 电池活性物质合成前体配方
    • US09112225B2
    • 2015-08-18
    • US13470041
    • 2012-05-11
    • Lu YangMiaojun WangDongli Zeng
    • Lu YangMiaojun WangDongli Zeng
    • H01M4/60H01M4/04H01M4/48C01B13/18H01M10/052
    • H01M4/48C01B13/185H01M10/052Y02P20/133
    • Compositions and methods of forming battery active materials are provided. A solution of battery active metal cations and reactive anions may be blended with a fuel to yield a precursor mixture usable for synthesizing a battery active material for deposition onto a substrate. The battery active metal cations include lithium, manganese, cobalt, nickel, iron, vanadium, and the like. Reactive anions include nitrate, acetate, citrate, tartrate, maleate, azide, amide, and other lower carboxylates. Suitable fuels, which may be water miscible, may include amino compounds. Alcohols and sugars may be added to adjust carbon content and fuel combustion characteristics. An exothermic reaction is performed to convert the metals into battery active oxides.
    • 提供了形成电池活性材料的组合物和方法。 电池活性金属阳离子和反应性阴离子的溶液可以与燃料共混以产生可用于合成用于沉积到基底上的电池活性材料的前体混合物。 电池活性金属阳离子包括锂,锰,钴,镍,铁,钒等。 活性阴离子包括硝酸盐,乙酸盐,柠檬酸盐,酒石酸盐,马来酸盐,叠氮化物,酰胺和其它低级羧酸盐。 可以与水混溶的合适的燃料可以包括氨基化合物。 可以加入醇和糖以调节碳含量和燃料燃烧特性。 进行放热反应以将金属转化成电池活性氧化物。