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1. 发明授权

US06300652B1 Memory cell configuration and method for its production 失效
标题翻译：存储单元配置及其生产方法
公开(公告)号：US06300652B1
公开(公告)日：2001-10-09
申请号：US08755456
申请日：1996-11-22
申请人： Lothar Risch , Franz Hofmann , Rainer Bruchhaus , Wolfram Wersing
发明人： Lothar Risch , Franz Hofmann , Rainer Bruchhaus , Wolfram Wersing
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A memory cell configuration and a method for its production include stacked capacitors and use a vertical storage capacitor having a ferroelectric or paraelectric storage dielectric. In order to produce the storage capacitor, a dielectric layer for the storage dielectric is produced over the whole area. The dielectric layer is subsequently structured and first electrodes and second electrodes for the storage capacitors are formed. The invention is suitable for Gbit DRAMs and for nonvolatile memories.
摘要翻译：存储单元配置及其制造方法包括堆叠电容器，并且使用具有铁电或顺电存储电介质的垂直存储电容器。为了制造存储电容器，在整个区域上产生用于存储电介质的电介质层。随后构造电介质层，形成用于存储电容器的第一电极和第二电极。本发明适用于Gbit DRAM和非易失性存储器。

2. 发明授权

US07180115B1 DRAM cell structure with tunnel barrier 有权
标题翻译：具有隧道势垒的DRAM单元结构
公开(公告)号：US07180115B1
公开(公告)日：2007-02-20
申请号：US10130441
申请日：2000-11-14
申请人： Franz Hofmann , Wolfgang Roesner , Lothar Risch , Till Schloesser
发明人： Franz Hofmann , Wolfgang Roesner , Lothar Risch , Till Schloesser
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10891 , H01L27/1203
摘要： The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.
摘要翻译：本发明涉及一种具有第一源极/漏极区域（S / D 1），与其相邻的沟道区域（KA），与其相邻的第二源极/漏极区域（S / D 2），栅极电介质和栅电极。电容器的第一电容器电极（SP）连接到第一源极/漏极区域（S / D 1）。绝缘结构完全围绕电路装置的绝缘区域。至少第一电容器电极（SP）和第一源极/漏极区域（S / D 1）布置在绝缘区域中。电容器的第二源极/漏极区域（S / D 2）和第二电容器电极布置在绝缘区域的外部。绝缘结构防止第一电容器电极（SP）通过电容器的充电和放电之间的泄漏电流而失去电荷。布置在通道区域（KA）中的隧道势垒（T）是绝缘结构的一部分。将第一电容器电极（SP）与第二电容器电极分离的电容器电介质（KD）是绝缘结构的一部分。

3. 发明授权

US06518628B1 Integrated CMOS circuit configuration, and production of same 有权
标题翻译：集成CMOS电路配置，生产相同
公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
申请人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
发明人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译：一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

4. 发明授权

US06255684B1 DRAM cell configuration and method for its production 失效
标题翻译： DRAM单元配置及其生产方法
公开(公告)号：US06255684B1
公开(公告)日：2001-07-03
申请号：US09071798
申请日：1998-05-04
申请人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
发明人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.
摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。晶体管的第二源/漏区连接到存储节点。晶体管的栅电极具有由栅极氧化物邻接的正好两侧。可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

5. 发明授权

US6037209A Method for producing a DRAM cellular arrangement 有权
标题翻译：用于制造DRAM蜂窝装置的方法
公开(公告)号：US6037209A
公开(公告)日：2000-03-14
申请号：US254696
申请日：1999-03-15
申请人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
发明人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.
摘要翻译： PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

6. 发明授权

US07829892B2 Integrated circuit including a gate electrode 有权
标题翻译：集成电路包括栅电极
公开(公告)号：US07829892B2
公开(公告)日：2010-11-09
申请号：US11926653
申请日：2007-10-29
申请人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
发明人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
IPC分类号： H01L29/12
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅极电极将沟道层包围至少两个相对的侧面。

7. 发明授权

US06362502B1 DRAM cell circuit 有权
标题翻译： DRAM单元电路
公开(公告)号：US06362502B1
公开(公告)日：2002-03-26
申请号：US09692118
申请日：2000-10-19
申请人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
发明人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/1203 , H01L27/108 , H01L27/10876
摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.
摘要翻译：存储单元包含存储晶体管和转移晶体管。转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。控制栅电极通过第二电介质层与浮置栅电极隔离。存储晶体管的第一源/漏区连接到位线。存储器和转移晶体管优选地具有不同的导电类型。在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

8. 发明授权

US5998261A Method of producing a read-only storage cell arrangement 失效
标题翻译：制造只读存储单元布置的方法
公开(公告)号：US5998261A
公开(公告)日：1999-12-07
申请号：US973701
申请日：1997-12-08
申请人： Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider , Lothar Risch
发明人： Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider , Lothar Risch
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11517 , H01L27/115
摘要： An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.
摘要翻译： PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。第WO97 / 02599号公报日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。具有存储单元的单元阵列设置在半导体基板的主表面上。每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。多个基本上平行的带状沟槽设置在单元阵列中。垂直MOS晶体管布置在沟槽的侧面。存储单元在每种情况下都布置在沟槽的相对侧面上。

9. 发明授权

US5920099A Read-only memory cell array and process for manufacturing it 失效
标题翻译：只读存储单元阵列及其制造过程
公开(公告)号：US5920099A
公开(公告)日：1999-07-06
申请号：US913332
申请日：1997-09-11
申请人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
发明人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.
摘要翻译： PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。

10. 发明授权

US5710072A Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells 失效
标题翻译：包含自放大动态MOS晶体管存储单元的制造和布置方法
公开(公告)号：US5710072A
公开(公告)日：1998-01-20
申请号：US737236
申请日：1996-11-18
申请人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
发明人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10844 , H01L27/0629 , H01L27/108
摘要： To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.
摘要翻译： PCT No.PCT / EP95 / 01656 Sec。 371日期：1996年11月18日 102（e）1996年11月18日PCT PCT 1995年5月2日PCT公布。公开号WO95 / 31828 日期：1995年11月23日为了制造包含自放大动态MOS晶体管存储单元的布置，每个包括选择晶体管，存储晶体管和二极管结构，选择晶体管和存储晶体管通过公共节点串联连接，二极管结构连接在存储晶体管的公共节点和栅电极（10）之间，选择晶体管和存储晶体管形成为垂直MOS晶体管。为此，产生其中产生沟槽（5,6）并且设置有栅极电介质（7,8）和栅电极（9,10））的适当掺杂区（2,3,4）的垂直序列，特别是通过LPCVD外延或通过分子束外延。

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