专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06969189B2 LED backlight module 有权
标题翻译： LED背光模组
公开(公告)号：US06969189B2
公开(公告)日：2005-11-29
申请号：US10629731
申请日：2003-07-30
申请人： Liu-Chung Lee , Chih-Wei Lin
发明人： Liu-Chung Lee , Chih-Wei Lin
IPC分类号： F21K99/00 , F21V7/04 , H05K1/02 , H05K3/28
CPC分类号： H05K1/0274 , F21K9/00 , H05K3/284 , H05K2201/0108 , H05K2201/10106 , H05K2201/2054
摘要： An LED backlight module. The LED backlight module comprises a printed circuit board, a plurality of LEDs, and a light transmissive material. The LEDs are disposed on the printed circuit board. The light transmissive material is coated on the printed circuit board. Particularly, the LEDs are embedded in the light transmissive material and arranged in a matrix.
摘要翻译： LED背光模组 LED背光模块包括印刷电路板，多个LED和透光材料。 LED布置在印刷电路板上。透光材料涂覆在印刷电路板上。特别地，LED嵌入在透光材料中并且被布置成矩阵。

2. 发明授权

US08247245B2 Pixel structure and method for fabricating the same 有权
标题翻译：像素结构及其制造方法
公开(公告)号：US08247245B2
公开(公告)日：2012-08-21
申请号：US13047610
申请日：2011-03-14
申请人： Hsiang-Lin Lin , Liu-Chung Lee , Kuo-Yu Huang
发明人： Hsiang-Lin Lin , Liu-Chung Lee , Kuo-Yu Huang
IPC分类号： H01L29/72
CPC分类号： G02F1/136213 , G02F2001/136218
摘要： A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure.
摘要翻译：公开了像素结构。像素结构包括基板，具有至少一个端部形成在基板上的第一数据线，覆盖第一数据线并暴露第一数据线的端部的一部分的第一绝缘层，设置在第一数据线上的屏蔽电极绝缘层并与第一数据线重叠，形成在第一绝缘层上并电连接到第一数据线的暴露端的第二数据线，覆盖屏蔽电极和第二数据线的第二绝缘层，以及像素电极，形成在第二绝缘层上并与屏蔽电极重叠。本发明还提供了一种用于制造像素结构的方法。

3. 发明申请

US20120168743A1 THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20120168743A1
公开(公告)日：2012-07-05
申请号：US13097082
申请日：2011-04-29
申请人： Liu-Chung Lee , Hung-Che Ting , Chia-Yu Chen
发明人： Liu-Chung Lee , Hung-Che Ting , Chia-Yu Chen
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/7869 , H01L29/78693
摘要： A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.
摘要翻译：提供了包括栅极，栅极绝缘体，氧化物半导体沟道层，源极和漏极的薄膜晶体管（TFT）。栅极绝缘体覆盖栅极，而氧化物半导体沟道层配置在栅极绝缘体上并位于栅极上方。氧化物半导体沟道层包括位于第一子层上的第一子层和第二子层。第一子层的氧含量低于第二子层的氧含量。源极和漏极配置在第二子层的一部分上。此外，还提供了上述TFT的制造方法。

4. 发明授权

US08339559B2 Liquid crystal display unit structure including a patterned etch stop layer above a first data line segment 有权
标题翻译：液晶显示单元结构包括在第一数据线段之上的图案化蚀刻停止层
公开(公告)号：US08339559B2
公开(公告)日：2012-12-25
申请号：US13466195
申请日：2012-05-08
申请人： Liu-Chung Lee , Hsiang-Lin Lin , Kuo-Yu Huang
发明人： Liu-Chung Lee , Hsiang-Lin Lin , Kuo-Yu Huang
IPC分类号： G02F1/136 , G02F1/1333 , G02F1/1343 , H01L29/04 , H01L29/10 , H01L31/00 , H01L27/14 , H01L29/15 , H01L31/036
CPC分类号： G02F1/13458 , G02F1/136227 , G02F2001/136218 , H01L27/124 , H01L27/1255 , H01L27/1288
摘要： A liquid crystal display unit structure and the manufacturing method thereof are provided. The liquid crystal display unit structure comprises a patterned first metal layer with a first data line segment and a gate line on a substrate; a patterned dielectric layer covering the first data line and the gate line having a plurality of first openings and a second opening therein, a patterned etch stop layer having a first portion located above the first data line segment and a second portion; a patterned second metal layer including a common electrode line, a second data line segment, a source electrode and a drain electrode, wherein the first portion of the patterned etch stop layer is between the first data line segment and the common line; a patterned passivation layer and a patterned transparent conductive layer.
摘要翻译：提供了一种液晶显示单元结构及其制造方法。液晶显示单元结构包括在基板上具有第一数据线段和栅极线的图案化第一金属层; 覆盖第一数据线的图案化介电层和具有多个第一开口和第二开口的栅极线，具有位于第一数据线段上方的第一部分的图案化蚀刻停止层和第二部分; 图案化的第二金属层，包括公共电极线，第二数据线段，源电极和漏电极，其中图案化蚀刻停止层的第一部分在第一数据线段和公共线之间; 图案化钝化层和图案化的透明导电层。

5. 发明授权

US07981708B1 Method of fabricating pixel structure and method of fabricating organic light emitting device 有权
标题翻译：制造像素结构的方法和制造有机发光器件的方法
公开(公告)号：US07981708B1
公开(公告)日：2011-07-19
申请号：US12908872
申请日：2010-10-20
申请人： Liu-Chung Lee , Hung-Che Ting , Chia-Yu Chen
发明人： Liu-Chung Lee , Hung-Che Ting , Chia-Yu Chen
IPC分类号： H01L21/00
CPC分类号： H01L27/3248 , H01L27/1225 , H01L27/3262
摘要： A method of fabricating a pixel structure is provided. A gate electrode is formed on a substrate, and a dielectric layer is formed on the gate electrode. A patterned metal oxide semiconductor layer and a patterned metallic etching stop layer are formed on the dielectric layer above the gate electrode. A first conductive layer is formed to cover the patterned metallic etching stop layer and the dielectric layer. The first conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a source and a drain. A second conductive layer is formed to cover the source, the drain and the dielectric layer. The second conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a first electrode layer. The patterned metallic etching stop layer exposed between the source and the drain is removed.
摘要翻译：提供了一种制造像素结构的方法。在基板上形成栅电极，在栅电极上形成介电层。在栅电极上的电介质层上形成图案化的金属氧化物半导体层和图案化的金属蚀刻停止层。形成第一导电层以覆盖图案化的金属蚀刻停止层和电介质层。通过使用图案化的金属蚀刻停止层作为蚀刻停止层来形成第一导电层以形成源极和漏极。形成第二导电层以覆盖源极，漏极和介电层。通过使用图案化的金属蚀刻停止层作为蚀刻停止层来图案化第二导电层，以形成第一电极层。去除在源极和漏极之间暴露的图案化金属蚀刻停止层。

6. 发明申请

US20090167975A1 Liquid Crystal Display Unit Structure and Manufacturing Method Thereof 有权
标题翻译：液晶显示单元的结构及制造方法
公开(公告)号：US20090167975A1
公开(公告)日：2009-07-02
申请号：US12274775
申请日：2008-11-20
申请人： Liu-Chung Lee , Hsiang-Lin Lin , Kuo-Yu Huang
发明人： Liu-Chung Lee , Hsiang-Lin Lin , Kuo-Yu Huang
IPC分类号： G02F1/136 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136227 , G02F2001/136218 , H01L27/124 , H01L27/1255 , H01L27/1288
摘要： A liquid crystal display unit structure and the manufacturing method thereof are provided. The method comprises the following steps: forming a patterned first metal layer with a first data line segment and a lower gate pad on a substrate; forming a patterned dielectric layer covering the first data line and the lower gate pad having a plurality of first openings and a second opening therein, forming a patterned second metal layer including a common line, a second data line segment and a upper gate pad, wherein the upper gate pad is electrically connected to the lower gate pad through the first openings, and the second data line segment is electrically connected to the first data line segment through the first openings; finally forming a patterned passivation layer and a patterned transparent conductive layer.
摘要翻译：提供了一种液晶显示单元结构及其制造方法。该方法包括以下步骤：在衬底上形成具有第一数据线段和下栅极焊盘的图案化第一金属层; 形成覆盖所述第一数据线的图案化电介质层和所述下栅极焊盘，其中具有多个第一开口和第二开口，形成包括公共线，第二数据线段和上栅极焊盘的图案化第二金属层，其中所述上栅极焊盘通过所述第一开口电连接到所述下栅极焊盘，并且所述第二数据线段通过所述第一开口电连接到所述第一数据线段; 最后形成图案化的钝化层和图案化的透明导电层。

7. 发明申请

US20070042537A1 Method of manufacturing a thin film transistor matrix substrate 有权
标题翻译：制造薄膜晶体管矩阵基板的方法
公开(公告)号：US20070042537A1
公开(公告)日：2007-02-22
申请号：US11359947
申请日：2006-02-22
申请人： Liu-Chung Lee
发明人： Liu-Chung Lee
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L27/124
摘要： A method of manufacturing a thin film transistor matrix substrate is provided. The first photo-mask process is used to define a gate electrode and a signal electrode. The second photo-mask process is used to obtain different thickness of a PR layer in different regions for forming a channel, gate electrode through holes, signal electrode through holes and conductive pads. The third photo-mask process is used to define a source, a drain, an upper signal electrode, a pixel electrode, gate electrode pads and signal electrode pads.
摘要翻译：提供了制造薄膜晶体管矩阵基板的方法。第一光掩模工艺用于限定栅电极和信号电极。第二光掩模工艺用于获得用于形成通道，栅电极通孔，信号电极通孔和导电焊盘的不同区域中PR层的不同厚度。第三光掩模工艺用于定义源极，漏极，上部信号电极，像素电极，栅极电极焊盘和信号电极焊盘。

8. 发明授权

US08647934B2 Thin film transistor and fabricating method thereof 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08647934B2
公开(公告)日：2014-02-11
申请号：US13097082
申请日：2011-04-29
申请人： Liu-Chung Lee , Hung-Che Ting , Chia-Yu Chen
发明人： Liu-Chung Lee , Hung-Che Ting , Chia-Yu Chen
IPC分类号： H01L21/84
CPC分类号： H01L29/7869 , H01L29/78693
摘要： A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.
摘要翻译：提供了包括栅极，栅极绝缘体，氧化物半导体沟道层，源极和漏极的薄膜晶体管（TFT）。栅极绝缘体覆盖栅极，而氧化物半导体沟道层配置在栅极绝缘体上并位于栅极上方。氧化物半导体沟道层包括位于第一子层上的第一子层和第二子层。第一子层的氧含量低于第二子层的氧含量。源极和漏极配置在第二子层的一部分上。此外，还提供了上述TFT的制造方法。

9. 发明授权

US08581259B2 Displaying device with photocurrent-reducing structure and method of manufacturing the same 有权
标题翻译：具有光电流降低结构的显示装置及其制造方法
公开(公告)号：US08581259B2
公开(公告)日：2013-11-12
申请号：US11254726
申请日：2005-10-21
申请人： Tung-Yu Chen , Liu-Chung Lee
发明人： Tung-Yu Chen , Liu-Chung Lee
IPC分类号： H01L27/14 , H01L29/04 , H01L29/15 , H01L31/036
CPC分类号： H01L29/66765
摘要： A displaying device includes a substrate, a gate electrode formed on the substrate, a gate insulating layer, a gate a-Si region covering the gate electrode, a source metal region, a drain metal region, a data-line (DL) metal region, a passivation layer and a conductive layer. The gate a-Si region is formed on the gate insulating layer. The source and drain metal regions are formed on the gate a-Si region. The DL metal region is formed on the gate insulating layer and separated from the drain metal region at an interval. The passivation layer formed on the gate insulating layer covers the source, drain, and DL metal regions. The first and second vias of the passivation layer expose partial surfaces of the DL and drain metal regions respectively. The conductive layer formed on the passivation layer covers the first and second vias for electrically connecting the DL and drain metal regions.
摘要翻译：显示装置包括基板，形成在基板上的栅极电极，栅极绝缘层，覆盖栅电极的栅极a-Si区域，源极金属区域，漏极金属区域，数据线（DL）金属区域，钝化层和导电层。栅极a-Si区域形成在栅极绝缘层上。源极和漏极金属区域形成在栅极a-Si区域上。 DL金属区域形成在栅极绝缘层上，并且与漏极金属区域间隔开。形成在栅极绝缘层上的钝化层覆盖源极，漏极和DL金属区域。钝化层的第一和第二通孔分别暴露DL和漏极金属区域的部分表面。形成在钝化层上的导电层覆盖用于电连接DL和漏极金属区域的第一和第二通孔。

10. 发明申请

US20120235138A1 MASK LEVEL REDUCTION FOR MOFET 有权
标题翻译：屏蔽层减少MOFET
公开(公告)号：US20120235138A1
公开(公告)日：2012-09-20
申请号：US13481781
申请日：2012-05-26
申请人： Chan-Long Shieh , Gang Yu , Fatt Foong , Liu-Chung Lee
发明人： Chan-Long Shieh , Gang Yu , Fatt Foong , Liu-Chung Lee
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1225
摘要： A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.
摘要翻译：制造具有减小的掩模操作的TFT和IPS的方法包括基板，栅极，栅极上的栅极电介质层和周围的衬底表面以及栅极电介质上的半导体金属氧化物。沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 S / D金属层在通道保护层和暴露的半导体金属氧化物的一部分上被图案化以限定IPS区域。在S / D端子和IPS区域的相对侧上构图有机电介质材料。蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层以限定覆盖第一电极的第二IPS电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式