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1. 发明授权

US08309447B2 Method for integrating multiple threshold voltage devices for CMOS 有权
标题翻译：用于集成多个CMOS阈值电压器件的方法
公开(公告)号：US08309447B2
公开(公告)日：2012-11-13
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

2. 发明申请

US20110081765A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 有权
标题翻译：提高生产费用总额的方法
公开(公告)号：US20110081765A1
公开(公告)日：2011-04-07
申请号：US12571483
申请日：2009-10-01
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

3. 发明申请

US20120040522A1 METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS 有权
标题翻译：用于集成用于CMOS的多个阈值电压器件的方法
公开(公告)号：US20120040522A1
公开(公告)日：2012-02-16
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

4. 发明授权

US09093558B2 Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate 有权
标题翻译：使用全金属栅极集成多个阈值电压器件用于互补金属氧化物半导体
公开(公告)号：US09093558B2
公开(公告)日：2015-07-28
申请号：US13594772
申请日：2012-08-24
申请人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
发明人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译：提供了基板，其上形成有与第一区域互补的第一区域和第二区域。在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。在第一区域上去除第一个全金属栅极叠层，以产生结果。在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。第一和第二全金属栅极堆叠被封装。

5. 发明申请

US20140054717A1 INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE 有权
标题翻译：使用全金属栅组合多个金属氧化物半导体的多个阈值电压装置
公开(公告)号：US20140054717A1
公开(公告)日：2014-02-27
申请号：US13594772
申请日：2012-08-24
申请人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
发明人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
IPC分类号： H01L21/283 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译：提供了基板，其上形成有与第一区域互补的第一区域和第二区域。在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。在第一区域上去除第一个全金属栅极叠层，以产生结果。在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。第一和第二全金属栅极堆叠被封装。

6. 发明申请

US20120178236A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
标题翻译：提高生产费用总额的方法
公开(公告)号：US20120178236A1
公开(公告)日：2012-07-12
申请号：US13422138
申请日：2012-03-16
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

7. 发明申请

US20120126295A1 BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION 有权
标题翻译：无边界联系人选择选择性沉积
公开(公告)号：US20120126295A1
公开(公告)日：2012-05-24
申请号：US12952372
申请日：2010-11-23
申请人： Lisa F. Edge , Balasubramanian S. Haran
发明人： Lisa F. Edge , Balasubramanian S. Haran
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823871 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.
摘要翻译：可以使用自对准栅极帽电介质来形成与扩散区域的自对准接触，同时防止由于覆盖变化导致的栅极导体的电短路。在一个实施例中，可电镀或无电镀的金属被选择性地沉积在栅电极中的导电材料上，同时金属不沉积在电介质表面上。栅极顶部的金属部分被转换成包括金属和氧的栅极电介质。在另一个实施例中，在电介质表面上形成自组装单层，同时暴露栅电极的金属顶表面。在未被自组装单层覆盖的区域上形成包括电介质氧化物的栅极电介质。栅极电介质在形成通孔期间用作蚀刻停止结构，从而避免了在其中形成的接触通孔结构与栅电极之间的电短路。

8. 发明申请

US20130200467A1 DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE METAL DEVICES 有权
标题翻译：双金属镀层和双重栅极电压替代栅极金属器件
公开(公告)号：US20130200467A1
公开(公告)日：2013-08-08
申请号：US13367419
申请日：2012-02-07
申请人： Lisa F. Edge , Nathaniel Berliner , James John Demarest , Balasubramanian S. Haran
发明人： Lisa F. Edge , Nathaniel Berliner , James John Demarest , Balasubramanian S. Haran
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L29/49 , H01L21/28088 , H01L21/82345 , H01L21/823842 , H01L27/088 , H01L29/66545
摘要： A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
摘要翻译：公开了用于形成双金属填充物的结构和方法以及用于替换栅极金属器件的双阈值电压。使用涉及钛和铝的选择性沉积方法来形成具有不同填充金属和不同功函数金属的两个相邻晶体管，从而能够在相邻晶体管中实现不同的阈值电压。

9. 发明授权

US08796128B2 Dual metal fill and dual threshold voltage for replacement gate metal devices 有权
标题翻译：用于更换栅极金属器件的双金属填充和双阈值电压
公开(公告)号：US08796128B2
公开(公告)日：2014-08-05
申请号：US13367419
申请日：2012-02-07
申请人： Lisa F. Edge , Nathaniel Berliner , James John Demarest , Balasubramanian S. Haran , Raymond J. Donohue
发明人： Lisa F. Edge , Nathaniel Berliner , James John Demarest , Balasubramanian S. Haran , Raymond J. Donohue
IPC分类号： H01L21/28 , H01L27/088
CPC分类号： H01L29/49 , H01L21/28088 , H01L21/82345 , H01L21/823842 , H01L27/088 , H01L29/66545
摘要： A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
摘要翻译：公开了用于形成双金属填充物的结构和方法以及用于替换栅极金属器件的双阈值电压。使用涉及钛和铝的选择性沉积方法来形成具有不同填充金属和不同功函数金属的两个相邻晶体管，从而能够在相邻晶体管中实现不同的阈值电压。

10. 发明授权

US08232607B2 Borderless contact for replacement gate employing selective deposition 有权
标题翻译：采用选择性沉积的替代栅极的无边界接触
公开(公告)号：US08232607B2
公开(公告)日：2012-07-31
申请号：US12952372
申请日：2010-11-23
申请人： Lisa F. Edge , Balasubramanian S. Haran
发明人： Lisa F. Edge , Balasubramanian S. Haran
IPC分类号： H01L21/02
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823871 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.
摘要翻译：可以使用自对准栅极帽电介质来形成与扩散区域的自对准接触，同时防止由于覆盖变化导致的栅极导体的电短路。在一个实施例中，可电镀或无电镀的金属被选择性地沉积在栅电极中的导电材料上，同时金属不沉积在电介质表面上。栅极顶部的金属部分被转换成包括金属和氧的栅极电介质。在另一个实施例中，在电介质表面上形成自组装单层，同时暴露栅电极的金属顶表面。在未被自组装单层覆盖的区域上形成包括电介质氧化物的栅极电介质。栅极电介质在形成通孔期间用作蚀刻停止结构，从而避免了在其中形成的接触通孔结构与栅电极之间的电短路。

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