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1. 发明授权

US06373098B1 Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device 有权
标题翻译：具有通过选择性外延生长形成沟槽壁的沟槽浇口装置和用于形成装置的工艺
公开(公告)号：US06373098B1
公开(公告)日：2002-04-16
申请号：US09318334
申请日：1999-05-25
申请人： Linda S. Brush , Jun Zeng , Christopher B. Kocon
发明人： Linda S. Brush , Jun Zeng , Christopher B. Kocon
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/42308 , H01L29/66348 , H01L29/7397 , H01L29/7813
摘要： An improved trench-gated power device comprises a substrate having an overlying layer of epitaxial material disposed on an upper layer of the substrate, well regions containing source and body regions, a trench gate, and a drain region. The improvement comprises a gate trench having beneficially smooth sidewalls that comprise selectively grown epitaxial material and body regions that are recessed with respect to adjacent source regions. In a process for forming an improved trench-gated power device, a dielectric layer having an upper surface and thickness and width dimensions that substantially correspond to the height and width dimensions of a gate trench is formed on an upper layer of the substrate. A layer of epitaxial material is grown on the upper layer of the substrate and the dielectric layer and planarized to be substantially coplanar with the upper surface of the dielectric layer, which is then removed, thereby forming gate trench sidewalls that comprise selectively grown epitaxial material. The process further comprises lining the trench with a dielectric material and substantially filling the lined trench with a conductive material, thereby forming a trench gate, and forming well, body, and source regions in the planarized epitaxial material.
摘要翻译：改进的沟槽门控功率器件包括具有设置在衬底的上层上的外延材料的重叠层的衬底，包含源极和体区的阱区，沟槽栅极和漏极区。该改进包括具有有利的平滑侧壁的栅极沟槽，其包括选择性地生长的外延材料和相对于相邻源极区域凹陷的主体区域。在用于形成改进的沟槽门控功率器件的工艺中，在衬底的上层上形成具有上表面的电介质层和基本对应于栅极沟槽的高度和宽度尺寸的厚度和宽度尺寸。在衬底的上层和电介质层上生长一层外延材料，并将其平坦化为与电介质层的上表面基本上共面，然后将其除去，从而形成包含选择性生长的外延材料的栅沟槽侧壁。该工艺还包括用介电材料衬套沟槽，并用导电材料基本上填充衬里的沟槽，从而形成沟槽栅极，并在平坦化的外延材料中形成阱，体和源极区。

2. 发明授权

US06445035B1 Power MOS device with buried gate and groove 有权
标题翻译：功率MOS器件具有掩埋栅极和沟槽
公开(公告)号：US06445035B1
公开(公告)日：2002-09-03
申请号：US09624533
申请日：2000-07-24
申请人： Jun Zeng , Gary M. Dolny , Christopher B. Kocon , Linda S. Brush
发明人： Jun Zeng , Gary M. Dolny , Christopher B. Kocon , Linda S. Brush
IPC分类号： H01L2994
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66363 , H01L29/7397 , H01L29/7455 , H01L29/7813
摘要： An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.
摘要翻译： MOS功率器件的衬底包括具有上表面和下面的漏极区的上层，设置在漏极区上的上层中的第一导电类型的阱区，以及多个间隔开的掩埋栅，包括从上层的上表面穿过阱区延伸到漏区的沟槽。每个沟槽包括衬在其表面上的绝缘材料，将其下部填充到基本上在上层的上表面下方的选定水平的导电材料，以及基本上填充沟槽其余部分的绝缘材料。第二导电类型的多个高掺杂源区被设置在邻近每个沟槽的上部的上层中，每个源区从上表面延伸到上层中的深度，以提供源区和沟槽中的导电材料。每个高掺杂源区域中的沟槽延伸穿过源区域进入阱区域并终止于最低点。第一导电类型的高掺杂体区域设置在与一个或多个凹槽的最低点相邻的阱区域中以及与沟槽穿透的相邻源极区域相邻的阱区域中。导电层设置在衬底上并与主体区域和源区域电接触。制造器件的工艺产生了MOS功率器件，其避免了沟道宽度的损失，并且在不牺牲器件耐用性和动态特性的情况下提供降低的沟道电阻。

3. 发明授权

US06638826B2 Power MOS device with buried gate 有权
标题翻译：功率MOS器件带埋栅
公开(公告)号：US06638826B2
公开(公告)日：2003-10-28
申请号：US10195984
申请日：2002-07-16
申请人： Jun Zeng , Gary M. Dolny , Christopher B. Kocon , Linda S. Brush
发明人： Jun Zeng , Gary M. Dolny , Christopher B. Kocon , Linda S. Brush
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66363 , H01L29/7397 , H01L29/7455 , H01L29/7813
摘要： An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.
摘要翻译： MOS功率器件的衬底包括具有上表面和下面的漏极区的上层，设置在漏极区上的上层中的第一导电类型的阱区，以及多个间隔开的掩埋栅，包括从上层的上表面穿过阱区延伸到漏区的沟槽。每个沟槽包括衬在其表面上的绝缘材料，将其下部填充到基本上在上层的上表面下方的选定水平的导电材料，以及基本上填充沟槽其余部分的绝缘材料。第二导电类型的多个高掺杂源区被设置在邻近每个沟槽的上部的上层中，每个源区从上表面延伸到上层中的深度，以提供源区和沟槽中的导电材料。每个高掺杂源区域中的沟槽延伸穿过源区域进入阱区域并终止于最低点。第一导电类型的高掺杂体区域设置在与一个或多个凹槽的最低点相邻的阱区域中以及与沟槽穿透的相邻源极区域相邻的阱区域中。导电层设置在衬底上并与主体区域和源区域电接触。制造器件的工艺产生了MOS功率器件，其避免了沟道宽度的损失，并且在不牺牲器件耐用性和动态特性的情况下提供降低的沟道电阻。

4. 发明授权

US06455379B2 Power trench transistor device source region formation using silicon spacer 失效
标题翻译：使用硅衬垫的功率沟槽晶体管器件源区域形成
公开(公告)号：US06455379B2
公开(公告)日：2002-09-24
申请号：US09799845
申请日：2001-03-06
申请人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
发明人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66378 , H01L29/66545 , H01L29/7397 , H01L29/749 , H01L29/7813
摘要： A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.
摘要翻译：功率沟槽MOS门控晶体管由栅极沟槽区域内的栅极源极构成。在创新的设备中，使用厚的氧化物（生长或沉积）来限定沟槽壁的高度。最初通过选择性外延生长和回蚀而形成体区。源区也通过选择性外延生长形成。身体最终通过选择性外延生长和回蚀而形成。从沟槽去除氧化物，沟槽壁被氧化以形成栅极氧化物，并且掺杂多晶硅填充沟槽以形成栅极。通过使用间隔物蚀刻形成源极区域，该工艺简化了功率沟槽门控器件的制造，并且提供了增加的接触表面积而不增加器件尺寸。

5. 发明授权

US06246090B1 Power trench transistor device source region formation using silicon spacer 有权
公开(公告)号：US06246090B1
公开(公告)日：2001-06-12
申请号：US09525182
申请日：2000-03-14
申请人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
发明人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66378 , H01L29/66545 , H01L29/7397 , H01L29/749 , H01L29/7813
摘要： A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

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