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1. 发明授权

US6134632A Controller that supports data merging utilizing a slice addressable memory array 失效
标题翻译：支持利用片可寻址存储器阵列进行数据合并的控制器
公开(公告)号：US6134632A
公开(公告)日：2000-10-17
申请号：US013094
申请日：1998-01-26
申请人： Lily Pao Looi , Sin Tan , John Urbanski , Christopher Van Beek
发明人： Lily Pao Looi , Sin Tan , John Urbanski , Christopher Van Beek
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0835 , G06F12/0804 , Y10S707/99942
摘要： A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line. Also provided is a method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory-write operation. The method includes setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to slices of a word line associated with the set slice enable bits in the slice-addressable random access memory buffer; and write-merging data from the modified cache line to slices of the word line not associated with the set slice-enable bits in the slice-addressable random access memory buffer.
摘要翻译：公开了一种包括片可寻址多端口存储器阵列的计算机系统。片可寻址的多端口存储器阵列提供了一种用于根据关联的片启用位阵列在存储器控制器中有效地数据合并的机制。存储器阵列的每个片段由片启用位分别指定，并且在写操作期间仅修改由片启用位指定的能够写入的字线的那些片。在随后的写合并操作中，修改了在写操作期间未被片使能位指定的写入字线的片，并且在前一写操作期间被修改的片不受影响，从而提供来自写入操作的数据的高效合并和来自写入合并操作的数据在单个字线中。还提供了当在存储器写入操作期间检测到高速缓存中的修改的行上的命中时，在计算机系统中保持高速缓存一致性的方法。该方法包括设置与通过存储器写入操作修改的高速缓存行的每个片段相关联的限幅使能位; 将数据写入与所述片可寻址随机存取存储器缓冲器中的所述设置片使能位相关联的字线的片; 以及从所述修改的高速缓存行将所述数据写入到与所述片可寻址随机存取存储器缓冲器中的所述设置的片使能位不相关联的字线的片。

2. 发明授权

US5996038A Individually resettable bus expander bridge mechanism 失效
标题翻译：单独复位总线扩展桥机构
公开(公告)号：US5996038A
公开(公告)日：1999-11-30
申请号：US13773
申请日：1998-01-26
申请人： Lily Pao Looi , Sin Tan , James Andrew Sutton, II
发明人： Lily Pao Looi , Sin Tan , James Andrew Sutton, II
IPC分类号： G06F13/40 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4045
摘要： A computer system including individually resettable bus expander bridges is described. A master bus controller provides an interface between at least one processor and at least one independently resettable bus expander bridge associated with one or more expansion buses. A bus expander bridge can be reset independently from the rest of the system when the master bus controller asserts a reset control signal that is applied to the bus expander bridge without affecting the operation of any other bus expander bridges or devices in the computer system not directly coupled to the expansion bus(es) being reset. When a reset control signal is asserted, the bus expander bridge being reset and the bus(es) associated with the bus expander bridge are reset to a default state. Once the reset process has had sufficient time for completion, the reset control signal is deasserted by the master bus controller and the bus expander bridge resumes operation.
摘要翻译：描述了包括单独可复位的总线扩展器桥的计算机系统。主总线控制器提供至少一个处理器与至少一个与一个或多个扩展总线相关联的可独立复位的总线扩展器桥接口。当主总线控制器断言施加到总线扩展器桥的复位控制信号，而不直接影响计算机系统中任何其他总线扩展器桥或器件的操作时，总线扩展器桥可以独立于系统的其余部分复位耦合到扩展总线被复位。当复位控制信号被断言时，总线扩展器桥被复位，并且与总线扩展器桥相关联的总线被复位到默认状态。一旦复位过程已经有足够的时间完成，复位控制信号被主总线控制器断开，总线扩展器桥恢复运行。

3. 发明授权

US08782456B2 Dynamic and idle power reduction sequence using recombinant clock and power gating 有权
标题翻译：使用重组时钟和电源门控的动态和空闲功率降低序列
公开(公告)号：US08782456B2
公开(公告)日：2014-07-15
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

4. 发明申请

US20110296222A1 DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING 有权
标题翻译：使用重构时钟和功率增益的动态和空闲功率降低序列
公开(公告)号：US20110296222A1
公开(公告)日：2011-12-01
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

5. 发明授权

US07093079B2 Snoop filter bypass 有权
标题翻译：窥探过滤器旁路
公开(公告)号：US07093079B2
公开(公告)日：2006-08-15
申请号：US10323200
申请日：2002-12-17
申请人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
发明人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082
摘要： Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.
摘要翻译：描述了用于处理包括多个高速缓存节点的计算设备的相干请求的机器可读介质，方法和装置。在一些实施例中，相干开关可以从请求的高速缓存节点接收对一行存储器的相干请求。基于是否启用窥探过滤器旁路模式，相干交换机可以进一步向一个或多个非请求高速缓存节点发出窥探请求。特别地，当不在窥探过滤器旁路模式时，相干开关可以从窥探过滤器获得一致性数据，并且可以基于从窥探过滤器获得的一致性数据向0个或更多个非请求缓存节点发出窥探请求。此外，在窥探过滤器旁路模式中的相干交换机可以绕过窥探过滤器并且可以向所有不请求的缓存代理发出窥探请求。

6. 发明授权

US09146610B2 Throttling integrated link 有权
标题翻译：节流综合链接
公开(公告)号：US09146610B2
公开(公告)日：2015-09-29
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32 , G06F13/42
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。还公开了其他实施例。

7. 发明授权

US09110666B2 Throttling integrated link 有权
公开(公告)号：US09110666B2
公开(公告)日：2015-08-18
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32 , G06F13/42
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

8. 发明申请

US20120079159A1 Throttling Integrated Link 有权
标题翻译：节流综合链路
公开(公告)号：US20120079159A1
公开(公告)日：2012-03-29
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。还公开了其他实施例。

9. 发明申请

US20110296216A1 INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB 有权
标题翻译：处理器和输入/输出总线的集成
公开(公告)号：US20110296216A1
公开(公告)日：2011-12-01
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

10. 发明授权

US5930486A Method and device for gracious arbitration of access to a computer system resource 失效
标题翻译：用于访问计算机系统资源的亲和仲裁的方法和装置
公开(公告)号：US5930486A
公开(公告)日：1999-07-27
申请号：US707884
申请日：1996-09-09
申请人： Lily Pao Looi , Nitin Borkar , Frank Verhoorn
发明人： Lily Pao Looi , Nitin Borkar , Frank Verhoorn
IPC分类号： G06F13/364 , G06F13/362
CPC分类号： G06F13/364
摘要： A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.
摘要翻译：计算机系统包括优先权仲裁方案，其防止优先代理人对总线进行“占用”。计算机系统包括至少一个代理，至少一个优先级代理，系统资源和将代理，优先级代理和系统资源彼此耦合的总线。仲裁器耦合到总线，代理和优先级代理以从代理和优先级代理接收请求信号，并且将总线的控制权授予代理和优先级代理之一用于访问系统资源。一旦总线变为下一个可用，优先权代理就会在优先权代理人断言一个请求信号时被控制总线。当代理人断言请求信号时，优先权代理将总线的总线放弃到总线带宽的预定部分。

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