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1. 发明授权

US07317632B2 Non-volatile memory storage device and controller therefor 有权
标题翻译：非易失性存储器及其控制器
公开(公告)号：US07317632B2
公开(公告)日：2008-01-08
申请号：US11341682
申请日：2006-01-30
申请人： Li-Pai Chen , Ming-Dar Chen , Hsiang-An Hsieh , Yen-Hsin Liu
发明人： Li-Pai Chen , Ming-Dar Chen , Hsiang-An Hsieh , Yen-Hsin Liu
IPC分类号： G11C11/34 , G11C5/34
CPC分类号： G11C16/30
摘要： A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory storage unit and a controller. The supply voltage booster boosts the lower supply voltage provided by the host device up to the higher operating voltage of the non-volatile memory. The controller adjusts the interface signal to a proper interface signal level by cooperating with the supply voltage and the operating voltage so as to avoid the interface from damage owing to an over high signal level or avoid the non-volatile memory unit from not correctly receiving signal due to an over low signal level.
摘要翻译：具有升高电源电压和信号电平功能的非易失性存储器装置可以采用具有比由主机设备提供的电源电压高的工作电压作为存储介质的非易失性存储器。非易失性存储器存储装置包括电源电压升压器，非易失性存储器存储单元和控制器。电源电压升压器将主机设备提供的较低电源电压升高到非易失性存储器的较高工作电压。控制器通过与电源电压和工作电压协调来将接口信号调整到适当的接口信号电平，以避免接口因过高信号电平而造成损坏，或避免非易失性存储单元不能正确接收信号由于信号电平过低。

2. 发明申请

US20070133299A1 Non-volatile memory storage device and controller therefor 有权
标题翻译：非易失性存储器及其控制器
公开(公告)号：US20070133299A1
公开(公告)日：2007-06-14
申请号：US11341682
申请日：2006-01-30
申请人： Li-Pai Chen , Ming-Dar Chen , Hsiang-An Hsieh , Yen-Hsin Liu
发明人： Li-Pai Chen , Ming-Dar Chen , Hsiang-An Hsieh , Yen-Hsin Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/30
摘要： A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory storage unit and a controller. The supply voltage booster boosts the lower supply voltage provided by the host device up to the higher operating voltage of the non-volatile memory. The controller adjusts the interface signal to a proper interface signal level by cooperating with the supply voltage and the operating voltage so as to avoid the interface from damage owing to an over high signal level or avoid the non-volatile memory unit from not correctly receiving signal due to an over low signal level.
摘要翻译：具有升高电源电压和信号电平功能的非易失性存储器装置可以采用具有比由主机设备提供的电源电压高的工作电压作为存储介质的非易失性存储器。非易失性存储器存储装置包括电源电压升压器，非易失性存储器存储单元和控制器。电源电压升压器将主机设备提供的较低电源电压升高到非易失性存储器的较高工作电压。控制器通过与电源电压和工作电压协调来将接口信号调整到适当的接口信号电平，以避免接口因过高信号电平而造成损坏，或避免非易失性存储单元不能正确接收信号由于信号电平过低。

3. 发明授权

US09153506B2 System and method for through silicon via yield 有权
标题翻译：通过硅产量的系统和方法
公开(公告)号：US09153506B2
公开(公告)日：2015-10-06
申请号：US13542896
申请日：2012-07-06
申请人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
发明人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
IPC分类号： G06F19/00 , H01L21/66 , H01L21/768
CPC分类号： H01L22/20 , H01L21/76898 , H01L22/12
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
摘要翻译：本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤中识别动作。

4. 发明申请

US20140011301A1 System and Method for Through Silicon Via Yield 有权
标题翻译：通过产量的硅的系统和方法
公开(公告)号：US20140011301A1
公开(公告)日：2014-01-09
申请号：US13542896
申请日：2012-07-06
申请人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
发明人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , H01L21/76898 , H01L22/12
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
摘要翻译：本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤识别动作。

5. 发明申请

US20130067142A1 FLASH MEMORY STORAGE DEVICE AND METHOD OF JUDGING PROBLEM STORAGE REGIONS THEREOF 审中-公开
标题翻译：闪速存储器存储器及其判定方法
公开(公告)号：US20130067142A1
公开(公告)日：2013-03-14
申请号：US13425990
申请日：2012-03-21
申请人： Young-Joon Choi , Kuo-Chung Liao , Yen-Hsin Liu , Chiang-Chang Hsien , Yun-Hui Wang , Chih-Ming Hsu
发明人： Young-Joon Choi , Kuo-Chung Liao , Yen-Hsin Liu , Chiang-Chang Hsien , Yun-Hui Wang , Chih-Ming Hsu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/073 , G06F11/0757 , G06F2212/7202 , G11C29/08 , G11C2029/0401 , G11C2029/0409
摘要： A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.
摘要翻译：一种判断适用于闪存存储装置的问题存储区域的方法包括以下步骤：向闪速存储器芯片发送写入命令以将写入的数据写入指定的存储寻呼; 当闪存芯片开始写入数据到指定的存储分页时，首次得到; 当闪存芯片完成写入数据到指定的存储分页时，第二次得到; 根据第一次和第二次计算写入时间; 如果写入时间不符合标准值，则将指定的存储分页标记为问题存储区域，并将写入的数据复制到备份分页; 更新映射表。

6. 发明申请

US20070220254A1 Secure digital memory devices and controllers thereof 审中-公开
标题翻译：安全的数字存储设备及其控制器
公开(公告)号：US20070220254A1
公开(公告)日：2007-09-20
申请号：US11496626
申请日：2006-08-01
申请人： Yen-Hsin Liu
发明人： Yen-Hsin Liu
IPC分类号： H04L9/00
CPC分类号： G11B27/105 , G06F11/1456 , G11B20/00086 , G11B20/1803 , G11B27/034 , G11B2220/61
摘要： A secure digital memory device comprising a first memory chip, a second memory chip, and a controller. The controller is coupled to the first and second memory chips and operates in an automatic backup mode of the secure digital memory device. In the automatic backup mode, the controller configures the first and second memory chips as main and backup memory partitions respectively. When data is written into the secure digital memory device, the controller writes the data to the main memory partition and into the backup memory partition to serve as backup data.
摘要翻译：一种安全数字存储设备，包括第一存储器芯片，第二存储器芯片和控制器。控制器耦合到第一和第二存储器芯片并在安全数字存储器件的自动备份模式下操作。在自动备份模式下，控制器将第一和第二存储器芯片分别配置为主备份存储器分区。当数据写入安全数字存储设备时，控制器将数据写入主存储器分区并进入备份存储器分区以作为备份数据。

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