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1. 发明授权

US06762795B1 Bi-directional capable bucket brigade circuit 有权
标题翻译：双向能力斗旅电路
公开(公告)号：US06762795B1
公开(公告)日：2004-07-13
申请号：US09479703
申请日：2000-01-07
申请人： Leonard P. Chen , Howard T. Chang , Eileen M. Herrin , Mary J. Hewitt , John L. Vampola
发明人： Leonard P. Chen , Howard T. Chang , Eileen M. Herrin , Mary J. Hewitt , John L. Vampola
IPC分类号： H04N314
CPC分类号： H04N5/37206 , H04N5/3743
摘要： A time delay integration circuit in which a number of unit cell inputs (101, 103, 105, 107) along with their respective switches (170, 171, 172, 173) are input to a bi-directional BBD circuit (110). The BBD circuit performs an SCA TDI with reduced ROIC circuitry and compatibility with standard LSI processing. The bi-directional BBD circuit has numerous pairs of MOSFETs (111, 112; 113, 114; 115, 116; 117, 118; 119, 120; 121, 122; 123, 124; 125, 126; 127, 128; 129, 130; 131, 132; 133, 134; 135, 136; 137, 138; 139, 140; 141, 142) connected in series and numerous storage capacitors (151, 152,153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166) having one of their terminals respectively connected between each of the MOSFET pairs and the other of their terminals alternately connected to clock phases Ø1 and Ø2. The gates of the MOSFETs in each pair are separated from the clock phases Ø1 and Ø2 and function respectively as screen gate and transfer clock for one direction of charge flow, and as transfer clock and screen gate for the other direction of charge flow. Transfer direction is changed by switching which MOSFET in a pair becomes clocked as a transfer gate and which becomes a screen gate.
摘要翻译：一种时间积分电路，其中多个单位单元输入（101,103,105,107）及其各自的开关（170,171,172,173）被输入到双向BBD电路（110）。 BBD电路执行SCA TDI，具有降低的ROIC电路和与标准LSI处理的兼容性。双向BBD电路具有多对MOSFET（111,112; 113,114; 115,116; 117,118; 119,120; 121,122; 123,124; 125,126; 127,128; 129，串联连接的多个存储电容器（151,152,153,154,155,156,157,158,159,130; 131,132,133,134,135,136,137,138,139,140,141,141,142,131,132,131,132,133,134,135,136,137,138,139,140,141,142,141,142,131,132,131,132,131,132,131,13 160,161,162,163,164,165,166），其端子中的一个分别连接在每个MOSFET对之间，并且其另一个端子交替地连接到时钟相位φ1和Ø2。每对MOSFET中的MOSFET的栅极与时钟相位φ1和φ2分开，并分别作为一个电荷流动方向的屏幕栅极和传输时钟，以及用于另一个电荷流动方向的传输时钟和屏幕栅极。转换方向通过切换成一对MOSFET变成时钟作为传输门并变成屏幕门而改变。

2. 发明授权

US06825877B1 Multiplex bucket brigade circuit 有权
标题翻译：多路斗旅电路
公开(公告)号：US06825877B1
公开(公告)日：2004-11-30
申请号：US09479699
申请日：2000-01-07
申请人： Mary J. Hewitt , John L. Vampola , Leonard P. Chen
发明人： Mary J. Hewitt , John L. Vampola , Leonard P. Chen
IPC分类号： H04N314
CPC分类号： H04N5/37206
摘要： A sensor chip assembly time delay integration circuit useful with image sensing arrays uses a duplex bucket brigade circuit (120) with two or more charge transfer paths, a number of capacitors (130, 133, 136) common to the charge transfer paths, and a number of capacitors (131, 132, 134, 135) specific to each of the charge transfer paths. Each of the charge transfer paths has a number of MOSFET transfer gates (122, 124, 126, 128; 123, 125, 127, 129) connected in series, and the common capacitors and the path-specific capacitors are alternately connected to the paths. Each of the common capacitors is controllably connected (112, 115, 118) either to a unit cell input circuit (113, 116, 119). a reset node (111, 114, 117), or an open circuit. The circuit operates by storing accumulated image sensor charges from alternate sensor lines on the path-specific capacitors. The common capacitors are reset and then connected to the unit cell input circuits to acquire a first set of image sensor charges. Charges stored on, for example, the capacitors of a particular path are then transferred to the common capacitors through transfer gates, in effect accumulating charge on the common capacitors. Then, charges are transferred from the common capacitors to the capacitors of the same particular path to again store the charges. The sequence of reset, charge acquisition, summation transfer, and storage transfer is repeated for each of the charge transfer paths.
摘要翻译：与图像感测阵列有用的传感器芯片组合时间延迟积分电路使用具有两个或更多个电荷传输路径的双工桶旅电路（120），电荷传输路径共用的多个电容器（130,133,136），以及每个电荷传输路径特有的电容器数目（131,132,134,135）。每个电荷传输路径具有串联连接的多个MOSFET传输门（122,124,126,128; 123,125,127,129），并且公共电容器和路径专用电容器交替地连接到路径。每个公共电容器被可控地连接到单元电池输入电路（113,116,119）上（112,115,118）。复位节点（111,114,117）或开路。电路通过将来自备用传感器线路的累积图像传感器电荷存储在路径特定电容器上来操作。公共电容器被复位，然后连接到单元电池输入电路以获取第一组图像传感器电荷。存储在例如特定路径的电容器上的电荷然后通过传输门传送到公共电容器，实际上在公共电容器上累积电荷。然后，电荷从公共电容器转移到相同特定路径的电容器，以再次存储电荷。为每个电荷传输路径重复复位，电荷获取，求和转移和存储传输的顺序。

3. 发明申请

US20070235655A1 Multi-layer pixellated gamma-ray detector 有权
标题翻译：多层像素化伽马射线探测器
公开(公告)号：US20070235655A1
公开(公告)日：2007-10-11
申请号：US11732610
申请日：2007-04-04
申请人： David R. Rhiger , Leonard P. Chen
发明人： David R. Rhiger , Leonard P. Chen
IPC分类号： G01T1/24
CPC分类号： G01T1/242 , G01T1/2928
摘要： A method and apparatus for detecting gamma-rays is provided, wherein the gamma-ray detector apparatus includes a plurality of detector elements arranged in a stacked configuration. Each of the plurality of detector elements may include, a detector wafer having at least one anode separated from a cathode via a wafer material, wherein the wafer material includes a wafer material thickness d, and a wafer interface, wherein the wafer interface is electrically connected to the at least one anode.
摘要翻译：提供了一种用于检测伽马射线的方法和装置，其中伽马射线检测器装置包括以堆叠配置布置的多个检测器元件。多个检测器元件中的每一个可以包括具有经由晶片材料与阴极分离的至少一个阳极的检测器晶片，其中晶片材料包括晶片材料厚度d和晶片接口，其中晶片接口电连接至少一个阳极。

4. 发明授权

US07978115B2 System and method for analog-to-digital conversion 有权
标题翻译：用于模数转换的系统和方法
公开(公告)号：US07978115B2
公开(公告)日：2011-07-12
申请号：US12497923
申请日：2009-07-06
申请人： Kenton T. Veeder , Micky Randall Harris , Leonard P. Chen
发明人： Kenton T. Veeder , Micky Randall Harris , Leonard P. Chen
IPC分类号： H03M1/38
CPC分类号： H03M1/164 , H03M1/56
摘要： A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.
摘要翻译：用于将模拟信号转换为数字信号的系统可以包括多个转换器级。一个转换器级可以包括乘法数模转换器（MDAC）和模数转换子转换器（ADSC）。 MDAC可以被配置为（i）从先前阶段接收表示数字信号的第一部分并对应于第一残余模拟信号的第一残余模拟信号和第一理想化数字信号; （ii）将第一理想化数字信号转换为理想模拟信号; 和（iii）基于第一残留模拟信号和理想模拟信号之间的差异输出第二残留模拟信号。 ADSC可以被配置为将第二残留模拟信号转换成表示数字信号的第二部分并对应于第二残留模拟信号的第二理想化数字信号，ADSC包括倾斜模数转换器。

5. 发明授权

US07439518B2 Multi-layer pixellated gamma-ray detector 有权
标题翻译：多层像素化伽马射线探测器
公开(公告)号：US07439518B2
公开(公告)日：2008-10-21
申请号：US11732610
申请日：2007-04-04
申请人： David R. Rhiger , Leonard P. Chen
发明人： David R. Rhiger , Leonard P. Chen
IPC分类号： G01T1/24
CPC分类号： G01T1/242 , G01T1/2928
摘要： A method and apparatus for detecting gamma-rays is provided, wherein the gamma-ray detector apparatus includes a plurality of detector elements arranged in a stacked configuration. Each of the plurality of detector elements may include, a detector wafer having at least one anode separated from a cathode via a wafer material, wherein the wafer material includes a wafer material thickness d, and a wafer interface, wherein the wafer interface is electrically connected to the at least one anode.
摘要翻译：提供了一种用于检测伽马射线的方法和装置，其中伽马射线检测器装置包括以堆叠配置布置的多个检测器元件。多个检测器元件中的每一个可以包括具有经由晶片材料与阴极分离的至少一个阳极的检测器晶片，其中晶片材料包括晶片材料厚度d和晶片接口，其中晶片接口电连接至少一个阳极。

6. 发明申请

US20110001647A1 System and Method for Analog-to-Digital Conversion 有权
标题翻译：用于模数转换的系统和方法
公开(公告)号：US20110001647A1
公开(公告)日：2011-01-06
申请号：US12497923
申请日：2009-07-06
申请人： Kenton T. Veeder , Micky Randall Harris , Leonard P. Chen
发明人： Kenton T. Veeder , Micky Randall Harris , Leonard P. Chen
IPC分类号： H03M1/72
CPC分类号： H03M1/164 , H03M1/56
摘要： A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.
摘要翻译：用于将模拟信号转换为数字信号的系统可以包括多个转换器级。一个转换器级可以包括乘法数模转换器（MDAC）和模数转换子转换器（ADSC）。 MDAC可以被配置为（i）从先前阶段接收表示数字信号的第一部分并对应于第一残余模拟信号的第一残余模拟信号和第一理想化数字信号; （ii）将第一理想化数字信号转换为理想模拟信号; 和（iii）基于第一残留模拟信号和理想模拟信号之间的差异输出第二残留模拟信号。 ADSC可以被配置为将第二残留模拟信号转换成表示数字信号的第二部分并对应于第二残留模拟信号的第二理想化数字信号，ADSC包括倾斜模数转换器。

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