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1. 发明授权

US07684563B1 Apparatus and method for implementing a unified hash algorithm pipeline 有权
标题翻译：用于实现统一哈希算法流水线的装置和方法
公开(公告)号：US07684563B1
公开(公告)日：2010-03-23
申请号：US10968428
申请日：2004-10-19
申请人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
发明人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28
CPC分类号： H04L9/16 , G06F9/3895 , H04L9/0643 , H04L2209/125 , H04L2209/38
摘要： An apparatus and method for implementing a unified hash algorithm pipeline. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm is dynamically selectable from a plurality of hash algorithms, and where the hash logic comprises a plurality of pipeline stages each configured to compute a portion of the hash algorithm. The cryptographic unit may further include a word buffer configured to store the data block during computing by the hash logic.
摘要翻译：一种用于实现统一哈希算法流水线的装置和方法。在一个实施例中，密码单元可以包括哈希逻辑，其被配置为根据散列算法计算数据块的哈希值，其中散列算法可以从多个散列算法动态地选择，并且其中散列逻辑包括多个流水线级分别被配置为计算散列算法的一部分。加密单元还可以包括字缓冲器，其被配置为在由哈希逻辑计算期间存储数据块。

2. 发明申请

US20100329450A1 INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS 审中-公开
标题翻译：使用通用寄存器执行数据加密标准（DES）计算的说明
公开(公告)号：US20100329450A1
公开(公告)日：2010-12-30
申请号：US12494481
申请日：2009-06-30
申请人： Leonard D. Rarick , Christopher H. Olson , Gregory F. Grohoski
发明人： Leonard D. Rarick , Christopher H. Olson , Gregory F. Grohoski
IPC分类号： H04L9/06
CPC分类号： H04L9/0625 , H04L2209/122 , H04L2209/125
摘要： Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor.
摘要翻译：本发明的一些实施例提供一种处理器，其包括一组通用寄存器和至少一个执行单元。通用寄存器组中的每个通用寄存器至少为64位宽，执行单元支持一个或多个数据加密标准（DES）指令。具体地，执行单元可以支持用于执行DES置换操作和DES旋转操作的置换旋转指令。执行单元还可以支持执行DES循环操作的循环指令。由于DES指令使用通用寄存器而不是专用寄存器来执行DES特定操作，所以处理器的电路复杂度和面积减少。此外，在一些实施例中，由于DES指令需要至多两个操作数，所以指定操作数的位置所需的位数减少，从而使更多数量的指令由处理器支持。

3. 发明授权

US07720219B1 Apparatus and method for implementing a hash algorithm word buffer 有权
标题翻译：用于实现散列算法字缓冲器的装置和方法
公开(公告)号：US07720219B1
公开(公告)日：2010-05-18
申请号：US10968406
申请日：2004-10-19
申请人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
发明人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28
CPC分类号： H04L9/16 , G06F9/3895 , H04L9/0643 , H04L2209/125 , H04L2209/38
摘要： An apparatus and method for implementing a hash algorithm word buffer. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm includes a plurality of iterations, and where the data block includes a plurality of data words. The cryptographic unit may further include a word buffer comprising a plurality of data word positions and configured to store the data block during computing by the hash logic, where subsequent to the hash logic computing one of the iterations of the hash algorithm, the word buffer is further configured to linearly shift the data block by one or more data word positions according to the hash algorithm. The hash algorithm may be dynamically selectable from a plurality of hash algorithms.
摘要翻译：一种用于实现散列算法字缓冲器的装置和方法。在一个实施例中，密码单元可以包括哈希逻辑，其被配置为根据散列算法来计算数据块的哈希值，其中散列算法包括多个迭代，并且其中数据块包括多个数据字。加密单元还可以包括字缓冲器，该字缓冲器包括多个数据字位置，并且被配置为在散列逻辑的计算期间存储该数据块，其中在散列逻辑之后计算散列算法的迭代之一，字缓冲器还被配置为根据所述散列算法将所述数据块线性移位一个或多个数据字位置。散列算法可以从多个散列算法中动态地选择。

4. 发明授权

US07711955B1 Apparatus and method for cryptographic key expansion 有权
标题翻译：加密密钥扩展的装置和方法
公开(公告)号：US07711955B1
公开(公告)日：2010-05-04
申请号：US10939530
申请日：2004-09-13
申请人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
发明人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
IPC分类号： H04L9/32 , H04L9/00 , G06F7/38
CPC分类号： H04L9/0637 , G06F9/3851 , H04L9/0894 , H04L2209/125 , H04L2209/24
摘要： An apparatus and method for cryptographic key expansion. According to a first embodiment, a cryptographic unit may include key storage configured to store an expanded set of cipher keys for a cipher algorithm, and a key expansion pipeline comprising a plurality of pipeline stages. During a key expansion mode of operation, each pipeline stage may be configured to perform a corresponding step of generating a member of the expanded set of cipher keys according to a key expansion algorithm. During a cipher mode of operation, a portion of the key expansion pipeline may be configured to perform a step of the cipher algorithm.
摘要翻译：一种用于加密密钥扩展的装置和方法。根据第一实施例，密码单元可以包括被配置为存储用于密码算法的扩展密钥集合的密钥存储器和包括多个流水线级的密钥扩展流水线。在密钥扩展操作模式期间，每个流水线级可以被配置为执行根据密钥扩展算法生成扩展密钥集合的成员的对应步骤。在密码操作模式期间，密钥扩展流水线的一部分可以被配置为执行密码算法的步骤。

5. 发明授权

US07620821B1 Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software 有权
标题翻译：处理器包括通用和加密功能，其中加密操作对用户指定的软件可见
公开(公告)号：US07620821B1
公开(公告)日：2009-11-17
申请号：US11064595
申请日：2005-02-24
申请人： Gregory F. Grohoski , Christopher H. Olson , Leonard D. Rarick
发明人： Gregory F. Grohoski , Christopher H. Olson , Leonard D. Rarick
IPC分类号： G06F11/30
CPC分类号： G06F9/3851 , G06F9/3877 , G06F21/72
摘要： A processor including general-purpose and cryptographic functionality, in which cryptographic operations are visible to user-specified software. According to one embodiment, a processor may include instruction execution logic configured to execute instructions specified by a user of the processor, where the instructions are compliant with a general-purpose instruction set architecture. The processor may further include a cryptographic functional unit configured to implement a plurality of cryptographic operations, and further configured to process the cryptographic operations independently of the instruction execution logic. A subset of the instructions may be executable to cause individual ones of the cryptographic operations to be processed by the cryptographic functional unit.
摘要翻译：包括通用和加密功能的处理器，其中密码操作对于用户指定的软件是可见的。根据一个实施例，处理器可以包括被配置为执行由处理器的用户指定的指令的指令执行逻辑，其中指令符合通用指令集架构。处理器还可以包括被配置为实现多个密码操作的密码功能单元，并且还被配置为独立于指令执行逻辑来处理密码操作。指令的子集可以是可执行的，以使加密功能单元处理各个密码操作。

6. 发明授权

US08654970B2 Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm 有权
标题翻译：用于实现数据加密标准（DES）算法的指令支持的装置和方法
公开(公告)号：US08654970B2
公开(公告)日：2014-02-18
申请号：US12414755
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.
摘要翻译：包括用于实现数据加密标准（DES）块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括可以接收执行指令的密码单元。指令包括在ISA内定义的一个或多个DES指令。此外，DES指令可以由加密单元执行，以实现符合联邦信息处理标准出版物46-3（FIPS 46-3）的DES密码的部分。响应于接收到在ISA内定义的DES密钥扩展指令，密码单元可以从输入密钥生成DES密码密钥调度的一个或多个扩展密码密钥。

7. 发明授权

US08417961B2 Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC) 有权
标题翻译：用于执行用于执行循环冗余校验（CRC）的指令支持的装置和方法
公开(公告)号：US08417961B2
公开(公告)日：2013-04-09
申请号：US12725243
申请日：2010-03-16
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F11/30
CPC分类号： G06F9/3861 , G06F9/30007 , G06F9/30018 , G06F9/3851 , G06F9/3885 , G06F11/1004 , G06F21/72 , H03M13/09 , H03M13/096 , H03M13/158 , H04L1/0041 , H04L1/0061 , H04L9/0631
摘要： Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41. In some embodiments, the first instance of the CRC instruction specifies an initial value to be used in performing the first CRC operation, the set of data, and a storage location in which the cryptographic unit is configured to store the checksum value produced by the first CRC operation.
摘要翻译：涉及包括执行循环冗余校验（CRC）操作的指令支持的处理器的技术。处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括被配置为接收包括在ISA内定义的循环冗余校验（CRC）指令的第一实例的指令的加密单元，其中CRC指令的第一实例可由密码单元执行以执行第一CRC操作在产生校验和值的一组数据上。在一个实施例中，密码单元被配置为使用生成器多项式0x11EDC6F41生成校验和值。在一些实施例中，CRC指令的第一实例指定用于执行第一CRC操作，数据集合以及存储位置的初始值，其中密码单元被配置为存储由第一个CRC操作产生的校验和值 CRC操作。

8. 发明授权

US08356185B2 Apparatus and method for local operand bypassing for cryptographic instructions 有权
标题翻译：用于加密指令的本地操作数旁路的装置和方法
公开(公告)号：US08356185B2
公开(公告)日：2013-01-15
申请号：US12575832
申请日：2009-10-08
申请人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
发明人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
IPC分类号： G06F9/312 , G06F21/00
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/3826 , G06F9/3873 , G06F21/72 , H04L9/0637 , H04L2209/12 , H04L2209/125 , H04L2209/24
摘要： A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.
摘要翻译：处理器可以包括被配置为发出用于执行的指令的硬件指令获取单元和被配置为接收用于执行的指令的硬件功能单元，其中所述指令包括加密指令和非加密指令。功能单元可以包括被配置为执行具有相应的加密执行等待时间的加密指令的密码执行流水线，以及配置成执行非加密指令的非加密执行流水线，该非加密执行流水线的长度大于加密执行延迟。功能单元还可以包括局部旁路网络，其被配置为将由密码执行流水线产生的结果旁路到在密码执行流水线内执行的依赖密码指令，使得依赖密码指令序列内的每个指令都可以用密码执行等待时间执行，并且其中加密执行流水线的结果不被旁路到处理器内的任何其他功能单元。

9. 发明申请

US20100250964A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE CAMELLIA CIPHER ALGORITHM 有权
标题翻译：用于实施CAMELLIA CIPHER算法的指导性支持的装置和方法
公开(公告)号：US20100250964A1
公开(公告)日：2010-09-30
申请号：US12414831
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30003 , G06F9/30007 , G06F9/30018 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.
摘要翻译：包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明书包括在ISA内定义的一个或多个Camellia指令。另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

10. 发明授权

US09317286B2 Apparatus and method for implementing instruction support for the camellia cipher algorithm 有权
标题翻译：用于实现山茶密码算法的指令支持的装置和方法
公开(公告)号：US09317286B2
公开(公告)日：2016-04-19
申请号：US12414831
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F9/30 , G06F9/38 , H04L9/06 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/30003 , G06F9/30007 , G06F9/30018 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.
摘要翻译：包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明书包括在ISA内定义的一个或多个Camellia指令。另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

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