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1. 发明授权

US08878298B2 Multiple Vt field-effect transistor devices 有权
标题翻译：多Vt场效应晶体管器件
公开(公告)号：US08878298B2
公开(公告)日：2014-11-04
申请号：US13346165
申请日：2012-01-09
申请人： Josephine B. Chang , Leland Chang , Renee T. Mo , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Renee T. Mo , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7856 , H01L29/66795
摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
摘要翻译：提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。

2. 发明申请

US20130260525A1 LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION 有权
标题翻译： SRAM扩展中的低延伸剂量植入
公开(公告)号：US20130260525A1
公开(公告)日：2013-10-03
申请号：US13438437
申请日：2012-04-03
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.
摘要翻译：一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。

3. 发明申请

US20130176769A1 8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES 有权
标题翻译：具有肖特基二极管的8晶体管SRAM单元设计
公开(公告)号：US20130176769A1
公开(公告)日：2013-07-11
申请号：US13345619
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C11/417 , G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.
摘要翻译：一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

4. 发明申请

US20130105897A1 Nanowire FET and FINFET Hybrid Technology 失效
标题翻译：纳米线FET和FINFET混合技术
公开(公告)号：US20130105897A1
公开(公告)日：2013-05-02
申请号：US13286311
申请日：2011-11-01
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/1211 , B82Y10/00 , B82Y40/00 , H01L21/3247 , H01L21/845 , H01L29/0673 , H01L29/42392 , H01L29/66469 , H01L29/78696
摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.
摘要翻译：提供了混合纳米线FET和FinFET器件及其制造方法。一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。提供了在BOX上具有活性层的晶片。有源层的第一区域变薄。有机平面化层沉积在有源层上。使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。使用第二硬掩模在活性层的第二区域中蚀刻金箔。形成围绕每个纳米线的至少一部分的第一栅极堆叠。形成第二栅极堆叠，覆盖每个散热片的至少一部分。在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

5. 发明授权

US08426917B2 Body-tied asymmetric P-type field effect transistor 有权
标题翻译：体系不对称P型场效应晶体管
公开(公告)号：US08426917B2
公开(公告)日：2013-04-23
申请号：US12683606
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66772
摘要： In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称P型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称P型场效应晶体管可用作对称P型场效应晶体管。

6. 发明授权

US08349670B2 Selective floating body SRAM cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US08349670B2
公开(公告)日：2013-01-08
申请号：US13045756
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥6个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

7. 发明申请

US20120182793A1 ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL 审中-公开
公开(公告)号：US20120182793A1
公开(公告)日：2012-07-19
申请号：US13430049
申请日：2012-03-26
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G11C11/40 , H01L27/092
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , H01L27/1203
摘要： A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

8. 发明授权

US08216907B2 Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance 有权
标题翻译：制造具有第一和第二硅侧壁以降低寄生电容的金属高K晶体管的工艺
公开(公告)号：US08216907B2
公开(公告)日：2012-07-10
申请号：US12880478
申请日：2010-09-13
申请人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
发明人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
IPC分类号： H01L21/336 , H01L21/338 , H01L21/8238 , H01L21/76 , H01L21/3205 , H01L21/4763 , H01L27/12 , H01L21/02 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/26586 , H01L21/28105 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656
摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.
摘要翻译：一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层; 选择性地仅去除第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

9. 发明申请

US20110191737A1 GENERATION OF ASYMMETRIC CIRCUIT DEVICES 有权
标题翻译：不对称电路设备的生成
公开(公告)号：US20110191737A1
公开(公告)日：2011-08-04
申请号：US12699621
申请日：2010-02-03
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于创建适当的块级形状以制造不对称场效应晶体管（FET）。在一个实施例中，该方法包括获得具有有源区域电平（RX）和栅极区域电平（PC）的集成电路设计，RX和PC电平中的每一个具有表示半导体区域的多个形状; 并且从RX和PC级形状定义具有多个SD级形状的新级别SD。该方法还包括确定哪些新形状是源区，哪些是形成漏区; 确定哪个源区域正在向上，哪些指向下？并复制向上指向的源区域的形状和指向下一个额定的定义的级别的源区域的形状。

10. 发明申请

US20110065244A1 ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE 有权
标题翻译：具有改进的抗电弧和电容的非对称FINFET器件
公开(公告)号：US20110065244A1
公开(公告)日：2011-03-17
申请号：US12559996
申请日：2009-09-15
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/66795
摘要： A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region.
摘要翻译：一种用于形成鳍状场效应晶体管（finFET）器件的方法包括：在衬底中形成翅片结构，形成垂直于翅片结构的栅极堆叠结构，并以一定角度（...）将离子注入到衬底中以形成源极区域和漏极区域，其中角度（θ）相对于源极区域是倾斜的。

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