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1. 发明授权

US08802574B2 Methods of making jogged layout routings double patterning compliant 有权
标题翻译：制作慢跑布局布线的方法双重图案化
公开(公告)号：US08802574B2
公开(公告)日：2014-08-12
申请号：US13418895
申请日：2012-03-13
申请人： Lei Yuan , Jongwook Kye
发明人： Lei Yuan , Jongwook Kye
IPC分类号： H01L21/302
CPC分类号： H01L21/0274 , G03F1/70
摘要： One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.
摘要翻译：本文公开的一种说明性方法包括创建包括具有连接第一和第二线部分的交叉区域的奇点运动特征的整体目标图案，其中，交叉区域具有大于第二尺寸的第一方向上的第一尺寸，横向于第一方向，将总体目标图案分解为第一子目标图案和第二子目标图案，其中每个子目标图案包括线路部分和交叉区域的第一部分，并且产生分别对应于第一和第二子目标图案的第一和第二组掩模数据。

2. 发明申请

US20140068543A1 METHOD TO ENHANCE DOUBLE PATTERNING ROUTING EFFICIENCY 有权
标题翻译：增强双重路线路由效率的方法
公开(公告)号：US20140068543A1
公开(公告)日：2014-03-06
申请号：US13603304
申请日：2012-09-04
申请人： Lei Yuan , Jongwook Kye
发明人： Lei Yuan , Jongwook Kye
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell.
摘要翻译：公开了一种使用DPT实现电路设计中的点动功能的方法，而不需要难以实现诸如针迹感知路由工具的工具。实施例包括：显示用于生成具有用于单层的多个掩模的IC的用户界面; 至少部分地使得包括填充单元的IC的单元放置的用户界面中的呈现; 并且将所述填充单元的一部分指定为路由区域，所述路由区域被配置为使得放置在所述路由区域中的路由可以与放置在所述填充单元之外的其他路由分解。

3. 发明申请

US20130298089A1 METHOD FOR INCREASING THE ROBUSTNESS OF A DOUBLE PATTERNING ROUTER USED TO MANUFACTURE INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于增加用于制造集成电路设备的双模式路由器的稳健性的方法
公开(公告)号：US20130298089A1
公开(公告)日：2013-11-07
申请号：US13465909
申请日：2012-05-07
申请人： Lei Yuan , Hidekazu Yoshida , Youngtag Woo , Jongwook Kye
发明人： Lei Yuan , Hidekazu Yoshida , Youngtag Woo , Jongwook Kye
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for increasing the robustness of a double patterning router used in the manufacture of integrated circuit devices that includes providing a set of original color rules defining an original color rule space, providing a set of integrated circuit designs defining a design space, providing a router processing engine, perturbing the original color rules to define a perturbed color rule space, applying the perturbed color rule space and the design space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and feeding back the exposed decomposition errors to enhance router processing engine development by reconfiguring the router processing engine in accordance with the exposed decomposition errors.
摘要翻译：一种用于增加用于制造集成电路器件的双重图案化路由器的鲁棒性的方法，其包括提供定义原始颜色规则空间的一组原始颜色规则，提供定义设计空间的一组集成电路设计，提供路由器处理引擎，扰乱原始颜色规则以定义扰动的颜色规则空间，将扰动的颜色规则空间和设计空间应用于路由器处理引擎以暴露双模式路由奇数周期分解错误，并反馈暴露的分解错误以增强通过根据暴露的分解错误重新配置路由器处理引擎来开发路由器处理引擎。

4. 发明申请

US20130295756A1 METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME 有权
标题翻译：使用本地互连处理方案形成半导体器件的联系方法
公开(公告)号：US20130295756A1
公开(公告)日：2013-11-07
申请号：US13465633
申请日：2012-05-07
申请人： Lei Yuan , Jin Cho , Jongwook Kye , Harry J. Levinson
发明人： Lei Yuan , Jin Cho , Jongwook Kye , Harry J. Levinson
IPC分类号： H01L21/28 , H01L21/283
CPC分类号： H01L21/823475 , H01L21/76895 , H01L23/485 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.
摘要翻译：本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层的局部互连结构位于分离第一和第二有源区域的隔离区域之上。该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。

5. 发明授权

US08324106B2 Methods for fabricating a photolithographic mask and for fabricating a semiconductor integrated circuit using such a mask 有权
标题翻译：制造光刻掩模的方法和使用这种掩模制造半导体集成电路的方法
公开(公告)号：US08324106B2
公开(公告)日：2012-12-04
申请号：US13079647
申请日：2011-04-04
申请人： Lei Yuan , Jongwook Kye , Harry J. Levinson
发明人： Lei Yuan , Jongwook Kye , Harry J. Levinson
IPC分类号： H01L21/311
CPC分类号： G03F1/38 , G03F1/70
摘要： Methods are provided for designing a photolithographic mask and for fabricating a semiconductor IC using such a mask. In accordance with one embodiment a method for fabricating a semiconductor IC includes determining a design target for a region within the IC. An initial mask geometry is determined for the region having a mask opening and a mask bias relative to the design target. A sub-resolution edge ring having a predetermined, fixed spacing to an edge of the mask opening is inserted into the mask geometry and a lithographic mask is generated. A material layer is applied overlying a semiconductor substrate upon which the IC is to be fabricated and a layer of photoresist is applied overlying the material layer. The layer of photoresist is exposed through the lithographic mask and is developed. A process step is then performed on the material layer using the layer of photoresist as a mask.
摘要翻译：提供了用于设计光刻掩模和使用这种掩模制造半导体IC的方法。根据一个实施例，制造半导体IC的方法包括确定IC内的区域的设计目标。对于具有掩模开口的区域和相对于设计目标的掩模偏置确定初始掩模几何形状。具有与掩模开口的边缘的预定的固定间隔的子分辨率边缘环被插入到掩模几何形状中，并且产生光刻掩模。应用覆盖在其上将要制造IC的半导体衬底上的材料层，并且覆盖在该材料层上的光致抗蚀剂层。光致抗蚀剂层通过光刻掩模曝光并显影。然后使用光致抗蚀剂层作为掩模在材料层上进行处理步骤。

6. 发明授权

US09268897B2 Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devices 有权
标题翻译：用于增加用于制造集成电路器件的双图案化路由器的鲁棒性的方法
公开(公告)号：US09268897B2
公开(公告)日：2016-02-23
申请号：US13465909
申请日：2012-05-07
申请人： Lei Yuan , Hidekazu Yoshida , Youngtag Woo , Jongwook Kye
发明人： Lei Yuan , Hidekazu Yoshida , Youngtag Woo , Jongwook Kye
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A process for manufacturing integrated circuit devices includes providing a set of original color rules defining an original color rule space and defining a design space. The improvement involves applying a perturbed color rule space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and reconfiguring the router processing engine in accordance with the exposed decomposition errors.
摘要翻译：一种用于制造集成电路器件的方法包括提供定义原始颜色规则空间并定义设计空间的一组原始颜色规则。改进之处在于将扰动的颜色规则空间应用于路由器处理引擎以暴露双模式路由奇数周期分解误差，并根据暴露的分解误差重新配置路由器处理引擎。

7. 发明授权

US08677291B1 Double patterning compatible colorless M1 route 有权
标题翻译：双重图案化兼容无色M1路线
公开(公告)号：US08677291B1
公开(公告)日：2014-03-18
申请号：US13646760
申请日：2012-10-08
申请人： Lei Yuan , Jongwook Kye , Mahbub Rashed , Qinglei Wang
发明人： Lei Yuan , Jongwook Kye , Mahbub Rashed , Qinglei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L25/00 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.
摘要翻译：公开了一种利用无色DPT M1路由放置的电路设计中的功能的方法，其保持高路由效率并保证目标模式和所得电路的M1可分解性。实施例包括：确定与IC中的第一和第二小区邻接的边界; 确定所述第一单元中面向所述第二单元中的第二边缘销的一侧的第一边缘销的一侧; 确定第一边缘销的侧面的至少一部分的第一垂直段和第二边缘销的侧面的至少一部分的第二垂直段; 指定所述第一垂直段和所述边界之间的区域作为路由区的第一部分; 并且指定所述第二垂直段和所述边界之间的区域作为所述路由区的第二部分。

8. 发明申请

US20130244427A1 METHODS OF MAKING JOGGED LAYOUT ROUTINGS DOUBLE PATTERNING COMPLIANT 有权
标题翻译：制作点阵布局路由的方法双重方式合规
公开(公告)号：US20130244427A1
公开(公告)日：2013-09-19
申请号：US13418895
申请日：2012-03-13
申请人： Lei Yuan , Jongwook Kye
发明人： Lei Yuan , Jongwook Kye
IPC分类号： G06F17/50 , H01L21/308
CPC分类号： H01L21/0274 , G03F1/70
摘要： One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.
摘要翻译：本文公开的一种说明性方法包括创建包括具有连接第一和第二线部分的交叉区域的奇点运动特征的整体目标图案，其中，交叉区域具有大于第二尺寸的第一方向上的第一尺寸，横向于第一方向，将总体目标图案分解为第一子目标图案和第二子目标图案，其中每个子目标图案包括线路部分和交叉区域的第一部分，并且产生分别对应于第一和第二子目标图案的第一和第二组掩模数据。

9. 发明申请

US20130175583A1 SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS 有权
标题翻译：具有接触电介质的半导体器件及相关制造方法
公开(公告)号：US20130175583A1
公开(公告)日：2013-07-11
申请号：US13345388
申请日：2012-01-06
申请人： Lei Yuan , Jin Cho , Jongwook Kye
发明人： Lei Yuan , Jin Cho , Jongwook Kye
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76888 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L29/66477 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.
摘要翻译：提供半导体器件结构的制造方法。制造半导体器件结构的一种方法包括形成覆盖形成在半导体衬底中的掺杂区域的第一介电材料的第一层，形成电连接到第一层内的掺杂区域的第一导电接触层，第一导电接触，形成覆盖在电介质盖上的第二电介质材料的第二层和覆盖在半导体衬底上的栅极结构，以及形成电连接到第二层内的栅极结构的第二导电接触。

10. 发明授权

US08765599B2 Semiconductor devices having dielectric caps on contacts and related fabrication methods 有权
标题翻译：具有接触电介质盖的半导体器件和相关的制造方法
公开(公告)号：US08765599B2
公开(公告)日：2014-07-01
申请号：US13345388
申请日：2012-01-06
申请人： Lei Yuan , Jin Cho , Jongwook Kye
发明人： Lei Yuan , Jin Cho , Jongwook Kye
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76888 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L29/66477 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.
摘要翻译：提供半导体器件结构的制造方法。制造半导体器件结构的一种方法包括形成覆盖形成在半导体衬底中的掺杂区域的第一介电材料的第一层，形成电连接到第一层内的掺杂区域的第一导电接触层，第一导电接触，形成覆盖在电介质盖上的第二电介质材料的第二层和覆盖在半导体衬底上的栅极结构，以及形成电连接到第二层内的栅极结构的第二导电接触。

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