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    • 8. 发明授权
    • On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise
    • 片内去耦电容和电源/接地网络线共同优化,以减少动态噪声
    • US07698677B2
    • 2010-04-13
    • US11731028
    • 2007-03-31
    • Min ZhaoRajendran Panda
    • Min ZhaoRajendran Panda
    • G06F17/50
    • G06F17/5077G06F17/5036
    • A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region (120) of the semiconductor circuit (100) design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level (220).
    • 半导体电力网络(100)去耦电容(分解)预算问题与布线增强问题共同优化,其中,该解决方案被配制为使要添加的总拆包或布线改变(线(420)的添加)最小化为 制作到网络(100)。 电压约束,可用空白和其他约束决定要添加的拆分量。 线增强和/或附加的折叠可以分布在半导体电路(100)设计的违反区域(120)中,以减少动态电源电压噪声,使得动态网络电压始终保持大于用户指定的阈值电压电平 (220)。
    • 9. 发明申请
    • On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise
    • 片内去耦电容和电源/接地网络线共同优化,以减少动态噪声
    • US20080244497A1
    • 2008-10-02
    • US11731028
    • 2007-03-31
    • Min ZhaoRajendran Panda
    • Min ZhaoRajendran Panda
    • G06F17/50
    • G06F17/5077G06F17/5036
    • A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region (120) of the semiconductor circuit (100) design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level (220).
    • 半导体电力网络(100)去耦电容(分解)预算问题与布线增强问题共同优化,其中,该解决方案被配制为使要添加的总拆包或布线改变(线(420)的添加)最小化为 制作到网络(100)。 电压约束,可用空白和其他约束决定要添加的拆分量。 线增强和/或附加的折叠可以分布在半导体电路(100)设计的违反区域(120)中,以减少动态电源电压噪声,使得动态网络电压始终保持大于用户指定的阈值电压电平 (220)。