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1. 发明授权

US5678016A Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization 失效
标题翻译：用于管理指令的执行的处理器和方法，所述指令确定在调度指令是否进行序列化之后
公开(公告)号：US5678016A
公开(公告)日：1997-10-14
申请号：US512741
申请日：1995-08-08
申请人： Lee E. Eisen , Robert T. Golla , Christopher H. Olson , Michael Putrino
发明人： Lee E. Eisen , Robert T. Golla , Christopher H. Olson , Michael Putrino
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384
摘要： A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction. In response to a determination that the second instruction need not be completed prior to successfully dispatching subsequent instructions, execution of the floating-point store instruction is initiated by computing the destination address within memory into which the operand of the floating-point store instruction is to be stored, thereby minimizing the delay in executing a floating-point store instruction.
摘要翻译：公开了一种用于管理包括具有多个浮点寄存器（FPR）的存储器和超标量处理器的数据处理系统内的浮点存储指令的执行的方法和装置。根据本发明，调度多个指令以供处理器执行，包括具有作为特定FPR的内容的操作数的浮点存储指令。确定特定FPR是否是用于以程序顺序在存储指令之前的第二指令的结果的目的地寄存器。如果是，则确定第二条指令是否必须在后续指令可以成功发送之前完成。响应于在成功发送后续指令之前必须完成第二条指令的确定，在完成第二条指令之后，浮点指令被取消并重新分配。响应于在成功发送后续指令之前不需要完成第二指令的确定，通过计算浮点存储指令的操作数所在的存储器内的目标地址来启动浮点存储指令的执行被存储，从而最小化执行浮点存储指令的延迟。

2. 发明授权

US08458446B2 Accessing a multibank register file using a thread identifier 有权
标题翻译：使用线程标识符访问多银行寄存器文件
公开(公告)号：US08458446B2
公开(公告)日：2013-06-04
申请号：US12570682
申请日：2009-09-30
申请人： Christopher H. Olson , Xiang Shan Li , Robert T. Golla
发明人： Christopher H. Olson , Xiang Shan Li , Robert T. Golla
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30127 , G06F9/3013 , G06F9/30141 , G06F9/3851 , G11C8/16
摘要： A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.
摘要翻译：处理器包括：指令获取单元，被配置为发出用于执行的指令，其中从多个线程中选择指令，其中每个给定指令具有对应的线程标识符，并且其中至少一些指令经由寄存器指定操作数身份标识。寄存器文件存储指令可用的操作数，并且可以包括几个存储体，每个存储体对应于寄存器标识符，并且包括与多个线程对应的多个条目，其中条目被配置为存储数据值。响应于接收到针对给定线程标识符读取特定寄存器标识符的请求，寄存器文件可以被配置为对给定的线程标识符进行解码以从对应于给定线程标识符的存储体检索条目。寄存器文件还可以从检索到的条目中选择与要输出的特定寄存器标识符对应的数据值。

3. 发明申请

US20110276783A1 THREAD FAIRNESS ON A MULTI-THREADED PROCESSOR WITH MULTI-CYCLE CRYPTOGRAPHIC OPERATIONS 有权
标题翻译：具有多周期运行的多线程处理器的螺纹公差
公开(公告)号：US20110276783A1
公开(公告)日：2011-11-10
申请号：US12773278
申请日：2010-05-04
申请人： Robert T. Golla , Christopher H. Olson , Gregory F. Grohoski
发明人： Robert T. Golla , Christopher H. Olson , Gregory F. Grohoski
IPC分类号： G06F9/38
CPC分类号： G06F9/5011 , G06F9/30007 , G06F9/3001 , G06F9/30018 , G06F9/384 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/3889 , G06F2209/507
摘要： Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing hardware resources for an appreciable amount of time. One example of a blocking type instruction is a Montgomery multiplication cryptographic instruction. Each thread can operate in a thread-based mode that allows the insertion of stall cycles during the execution of blocking instructions, during which other threads may utilize the previously blocked hardware resources. At times when multiple threads are scheduled to execute blocking instructions, the thread-based mode may be changed to increase throughput for these multiple threads. For example, the mode may be changed to disallow the insertion of stall cycles. Therefore, the time for sequential operation of the blocking instructions corresponding to the multiple threads may be reduced.
摘要翻译：在多线程处理器中有效执行操作的系统和方法。每个线程可以包括阻塞指令。阻塞指令阻止其他线程在相当长的时间内利用硬件资源。阻塞型指令的一个例子是蒙哥马利乘法加密指令。每个线程都可以以线程为基础的模式运行，允许在执行阻塞指令期间插入停滞周期，在此期间其他线程可能利用先前阻止的硬件资源。在多个线程被调度执行阻塞指令的时候，可以改变基于线程的模式，以增加这些多线程的吞吐量。例如，可以改变该模式以不允许插入失速循环。因此，可以减少对应于多个线程的阻塞指令的顺序操作的时间。

4. 发明授权

US08356185B2 Apparatus and method for local operand bypassing for cryptographic instructions 有权
标题翻译：用于加密指令的本地操作数旁路的装置和方法
公开(公告)号：US08356185B2
公开(公告)日：2013-01-15
申请号：US12575832
申请日：2009-10-08
申请人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
发明人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
IPC分类号： G06F9/312 , G06F21/00
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/3826 , G06F9/3873 , G06F21/72 , H04L9/0637 , H04L2209/12 , H04L2209/125 , H04L2209/24
摘要： A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.
摘要翻译：处理器可以包括被配置为发出用于执行的指令的硬件指令获取单元和被配置为接收用于执行的指令的硬件功能单元，其中所述指令包括加密指令和非加密指令。功能单元可以包括被配置为执行具有相应的加密执行等待时间的加密指令的密码执行流水线，以及配置成执行非加密指令的非加密执行流水线，该非加密执行流水线的长度大于加密执行延迟。功能单元还可以包括局部旁路网络，其被配置为将由密码执行流水线产生的结果旁路到在密码执行流水线内执行的依赖密码指令，使得依赖密码指令序列内的每个指令都可以用密码执行等待时间执行，并且其中加密执行流水线的结果不被旁路到处理器内的任何其他功能单元。

5. 发明授权

US07478225B1 Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor 有权
标题翻译：在多线程处理器中支持不同延迟指令流水线的装置和方法
公开(公告)号：US07478225B1
公开(公告)日：2009-01-13
申请号：US10881071
申请日：2004-06-30
申请人： Jeffrey S. Brooks , Christopher H. Olson , Robert T. Golla
发明人： Jeffrey S. Brooks , Christopher H. Olson , Robert T. Golla
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3873
摘要： An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a first and a second instruction from different ones of a plurality of threads during successive cycles. The processor may also include first and second execution units respectively configured to execute shorter-latency and longer-latency instructions and to respectively write shorter-latency or longer-latency instruction results to a result write port during a first or second writeback stage. The first writeback stage may occur a fewer number of cycles after instruction issue than the second writeback stage. The instruction fetch logic may be further configured to guarantee result write port access by the second execution unit during the second writeback stage by preventing the shorter-latency instruction from issuing during a cycle for which the first writeback stage collides with the second writeback stage.
摘要翻译：支持多线程处理器中可变延迟指令流水线的装置和方法。在一个实施例中，处理器可以包括指令提取逻辑，其被配置为在连续循环期间从多个线程中的不同线程发出第一和第二指令。处理器还可以包括第一和第二执行单元，其分别被配置为执行较短延迟和较长延迟的指令，并且在第一或第二回写阶段期间分别将较短等待时间或更长延迟的指令结果写入结果写入端口。指令发布后的第一个回写阶段可能发生的次数比第二个回写阶段少。指令提取逻辑可以被进一步配置为通过在第一写回阶段与第二回写阶段相冲突的周期期间防止短暂延迟指令发出来保证第二执行单元在第二写回阶段期间的结果写入端口访问。

6. 发明授权

US5583805A Floating-point processor having post-writeback spill stage 失效
标题翻译：浮点处理器具有回写后溢出阶段
公开(公告)号：US5583805A
公开(公告)日：1996-12-10
申请号：US352661
申请日：1994-12-09
申请人： Timothy A. Elliott , Robert T. Golla , Christopher H. Olson , Terence M. Potter
发明人： Timothy A. Elliott , Robert T. Golla , Christopher H. Olson , Terence M. Potter
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F7/49915
摘要： An apparatus for handling special cases outside of normal floating-point arithmetic functions is provided that is used in a floating-point unit used for calculating arithmetic functions. The floating-point unit generates an exponent portion and a mantissa portion and a writeback stage is coupled to the exponent portion and to the mantissa portion and is specifically used to handle the special cases outside the normal float arithmetic functions. A spill stage is also provided and is coupled to the writeback stage to receive a resultant exponent and mantissa. A register file unit is coupled to the writeback stage and the spill stage through a plurality of rename busses, which are used to carry results between the writeback stage and spill stage and the register file. The spill stage is serially coupled to the writeback stage so as to provide a smooth operation in the transition of operating on the results from the writeback stage for the exponent and mantissa. Each rename bus has a pair of tri-state buffers, one used to couple the rename bus to the writeback stage and the other used to couple the rename bus to the spill stage. The instruction dispatcher also provides location information for directing the results from the writeback stage and the spill stage before the result is completed.
摘要翻译：提供了用于处理正常浮点运算功能之外的特殊情况的装置，用于计算算术功能的浮点单元。浮点单元产生指数部分和尾数部分，并且回写阶段耦合到指数部分和尾数部分，并且专门用于处理普通浮点运算功能之外的特殊情况。还提供溢出阶段并且耦合到回写阶段以接收所得到的指数和尾数。寄存器文件单元通过多个重命名总线耦合到回写阶段和溢出阶段，这些总线用于在回写阶段和溢出阶段之间携带结果和寄存器文件。溢出级串联耦合到回写阶段，以便在针对指数和尾数的回写阶段的结果的转换中提供平滑的操作。每个重命名总线都有一对三态缓冲器，一个用于将重命名总线耦合到回写阶段，另一个用于将重命名总线耦合到溢出级。指令调度器还提供位置信息，用于在结果完成之前从写回阶段和溢出阶段引导结果。

7. 发明申请

US20110087895A1 APPARATUS AND METHOD FOR LOCAL OPERAND BYPASSING FOR CRYPTOGRAPHIC INSTRUCTIONS 有权
标题翻译：本地操作的装置和方法用于拼接指令
公开(公告)号：US20110087895A1
公开(公告)日：2011-04-14
申请号：US12575832
申请日：2009-10-08
申请人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
发明人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
IPC分类号： G06F21/00 , G06F9/30 , G06F9/312
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/3826 , G06F9/3873 , G06F21/72 , H04L9/0637 , H04L2209/12 , H04L2209/125 , H04L2209/24
摘要： A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.
摘要翻译：处理器可以包括被配置为发出用于执行的指令的硬件指令获取单元和被配置为接收用于执行的指令的硬件功能单元，其中所述指令包括加密指令和非加密指令。功能单元可以包括被配置为执行具有相应的加密执行等待时间的加密指令的密码执行流水线，以及配置成执行非加密指令的非加密执行流水线，该非加密执行流水线的长度大于加密执行延迟。功能单元还可以包括局部旁路网络，其被配置为将由密码执行流水线产生的结果旁路到在密码执行流水线内执行的依赖密码指令，使得依赖密码指令序列内的每个指令都可以用密码执行等待时间执行，并且其中加密执行流水线的结果不被旁路到处理器内的任何其他功能单元。

8. 发明申请

US20110078414A1 MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSORS EMPLOYING REGISTER WINDOWS 有权
标题翻译：多用途处理器和使用注册窗口的处理器的多个寄存器文件
公开(公告)号：US20110078414A1
公开(公告)日：2011-03-31
申请号：US12570682
申请日：2009-09-30
申请人： Christopher H. Olson , Xiang Shan Li , Robert T. Golla
发明人： Christopher H. Olson , Xiang Shan Li , Robert T. Golla
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30127 , G06F9/3013 , G06F9/30141 , G06F9/3851 , G11C8/16
摘要： A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.
摘要翻译：处理器包括：指令获取单元，被配置为发出用于执行的指令，其中从多个线程中选择指令，其中每个给定指令具有对应的线程标识符，并且其中至少一些指令经由寄存器指定操作数身份标识。寄存器文件存储指令可用的操作数，并且可以包括几个存储体，每个存储体对应于寄存器标识符，并且包括与多个线程对应的多个条目，其中条目被配置为存储数据值。响应于接收到针对给定线程标识符读取特定寄存器标识符的请求，寄存器文件可以被配置为对给定的线程标识符进行解码以从对应于给定线程标识符的存储体检索条目。寄存器文件还可以从检索到的条目中选择与要输出的特定寄存器标识符对应的数据值。

9. 发明申请

US20100257338A1 METHODS AND MECHANISMS TO SUPPORT MULTIPLE FEATURES FOR A NUMBER OF OPCODES 有权
标题翻译：支持多个操作系统的多种功能的方法和机制
公开(公告)号：US20100257338A1
公开(公告)日：2010-10-07
申请号：US12420054
申请日：2009-04-07
申请人： Lawrence A. Spracklen , Gregory F. Grohoski , Christopher H. Olson , Robert T. Golla
发明人： Lawrence A. Spracklen , Gregory F. Grohoski , Christopher H. Olson , Robert T. Golla
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30145 , G06F9/30101 , G06F9/30167 , G06F9/45504
摘要： Systems and methods for efficient instruction support of an multiple features for opcodes of an instruction set. A processor detects a fetched instruction of a computer program comprises an opcode corresponding to a plurality of functions. Each function corresponds to a different type of operation. The processor determines the received instruction corresponds to a feature requested by the computer program, such as a cryptographic algorithm. A determination is made as to whether hardware support exists for the feature. If hardware support exists for the feature, the instruction is executed on-chip by the hardware. Otherwise, software performs the operation corresponding to the instruction.
摘要翻译：用于指令集的操作码的多个特征的有效指令支持的系统和方法。处理器检测计算机程序的获取指令包括对应于多个功能的操作码。每个功能对应于不同类型的操作。处理器确定接收到的指令对应于计算机程序所请求的特征，例如加密算法。确定是否存在该功能的硬件支持。如果该功能存在硬件支持，则该指令由硬件在片上执行。否则，软件将执行与该指令相对应的操作。

10. 发明授权

US08560814B2 Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations 有权
标题翻译：具有多周期加密操作的多线程处理器上的线程公平性
公开(公告)号：US08560814B2
公开(公告)日：2013-10-15
申请号：US12773278
申请日：2010-05-04
申请人： Robert T. Golla , Christopher H. Olson , Gregory F. Grohoski
发明人： Robert T. Golla , Christopher H. Olson , Gregory F. Grohoski
IPC分类号： G06F9/30
CPC分类号： G06F9/5011 , G06F9/30007 , G06F9/3001 , G06F9/30018 , G06F9/384 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/3889 , G06F2209/507
摘要： Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing hardware resources for an appreciable amount of time. One example of a blocking type instruction is a Montgomery multiplication cryptographic instruction. Each thread can operate in a thread-based mode that allows the insertion of stall cycles during the execution of blocking instructions, during which other threads may utilize the previously blocked hardware resources. At times when multiple threads are scheduled to execute blocking instructions, the thread-based mode may be changed to increase throughput for these multiple threads. For example, the mode may be changed to disallow the insertion of stall cycles. Therefore, the time for sequential operation of the blocking instructions corresponding to the multiple threads may be reduced.
摘要翻译：在多线程处理器中有效执行操作的系统和方法。每个线程可以包括阻塞指令。阻塞指令阻止其他线程在相当长的时间内利用硬件资源。阻塞型指令的一个例子是蒙哥马利乘法加密指令。每个线程都可以以线程为基础的模式运行，允许在执行阻塞指令期间插入停滞周期，在此期间其他线程可能利用先前阻止的硬件资源。在多个线程被调度执行阻塞指令的时候，可以改变基于线程的模式，以增加这些多线程的吞吐量。例如，可以改变该模式以不允许插入失速循环。因此，可以减少对应于多个线程的阻塞指令的顺序操作的时间。

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