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1. 发明授权

US08856476B2 Systems, methods, and physical computer storage media to optimize data placement in multi-tiered storage systems 有权
标题翻译：系统，方法和物理计算机存储介质，以优化多层存储系统中的数据放置
公开(公告)号：US08856476B2
公开(公告)日：2014-10-07
申请号：US13531845
申请日：2012-06-25
申请人： Lawrence Y. Chiu , Yong Guo , Chao G. Li , Yang Liu , Paul Muench , Sangeetha Seshadri
发明人： Lawrence Y. Chiu , Yong Guo , Chao G. Li , Yang Liu , Paul Muench , Sangeetha Seshadri
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/02
CPC分类号： G06F12/02 , G06F17/30091
摘要： For optimizing data placement in a multi-tiered storage system, system configuration data and system performance data is collected. A plurality of data movement plans are generated, based in part on the system configuration data and the system performance data. A conflict between the plurality of data movement plans are arbitrated to form an execution plan. The data movement plans are performed according to the execution plan.
摘要翻译：为了优化多层存储系统中的数据放置，收集系统配置数据和系统性能数据。部分基于系统配置数据和系统性能数据生成多个数据移动计划。多个数据移动计划之间的冲突被仲裁以形成执行计划。数据移动计划根据执行计划执行。

2. 发明授权

US08838927B2 Systems, methods, and physical computer storage media to optimize data placement in multi-tiered storage systems 有权
标题翻译：系统，方法和物理计算机存储介质，以优化多层存储系统中的数据放置
公开(公告)号：US08838927B2
公开(公告)日：2014-09-16
申请号：US13117236
申请日：2011-05-27
申请人： Lawrence Y. Chiu , Yong Guo , Chao G. Li , Yang Liu , Paul Muench , Sangeetha Seshadri
发明人： Lawrence Y. Chiu , Yong Guo , Chao G. Li , Yang Liu , Paul Muench , Sangeetha Seshadri
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/02
CPC分类号： G06F12/02 , G06F17/30091
摘要： A system includes a data collector, a plurality of data placement optimizers, a data placement arbitrator, and a data mover. The data collector is configured to collect system configuration data and system performance data. The plurality of data placement optimizers are each configured to analyze the system configuration data and the system performance data for developing a corresponding data movement plan. The data placement arbitrator is configured to arbitrate conflicts between at least two data movement plans of generated by the plurality of data placement optimizers to form an execution plan. The data mover is configured to perform the data movement plans according to the execution plan.
摘要翻译：系统包括数据收集器，多个数据放置优化器，数据放置仲裁器和数据移动器。数据收集器配置为收集系统配置数据和系统性能数据。多个数据放置优化器被配置为分析系统配置数据和系统性能数据，以开发相应的数据移动计划。数据放置仲裁器被配置为仲裁由多个数据放置优化器生成的至少两个数据移动计划之间的冲突以形成执行计划。数据移动器被配置为根据执行计划执行数据移动计划。

3. 发明申请

US20060269030A1 Phase lock loop jitter measurement 审中-公开
标题翻译：锁相环抖动测量
公开(公告)号：US20060269030A1
公开(公告)日：2006-11-30
申请号：US11138151
申请日：2005-05-26
申请人： James Eckhardt , Paul Muench , George Smith
发明人： James Eckhardt , Paul Muench , George Smith
IPC分类号： H04L7/00
CPC分类号： H03L7/08
摘要： A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal. An analysis logic circuit is provided having a plurality of n inputs connected to the outputs of the latches. The analysis logic circuit analyzes the values on the latches to give a measure of jitter.
摘要翻译：一种抖动测量电路和方法，具有用于接收其测试抖动的参考信号的输入端，用于接收具有一系列周期的时钟信号的输入端和用于测量参考信号和时钟信号之间的延迟的测量电路在循环周期基础上，给出周期抖动测量的周期。测量电路包括多个n级，每级具有包括输入的延迟元件。第二和稍后的延迟元件的输入连接到前一级的输出，第一延迟元件具有用于接收参考信号的输入。 n个锁存器中的一个连接到对应的一个延迟元件的输入端。每个锁存器具有用于接收时钟信号的时钟输入端，以及当时钟输入由时钟信号的边沿计时时，用于锁存锁存器输入端的值的输出端。提供分析逻辑电路，其具有连接到锁存器的输出的多个n个输入。分析逻辑电路分析锁存器上的值以给出抖动的度量。

4. 发明申请

US20060269031A1 Phase Lock Loop Jitter Measurement 有权
标题翻译：锁相环抖动测量
公开(公告)号：US20060269031A1
公开(公告)日：2006-11-30
申请号：US11457161
申请日：2006-07-13
申请人： James Eckhardt , Paul Muench , George Smith
发明人： James Eckhardt , Paul Muench , George Smith
IPC分类号： H04L7/00
CPC分类号： H03L7/08
摘要： A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal. An analysis logic circuit is provided having a plurality of n inputs connected to the outputs of the latches. The analysis logic circuit analyzes the values on the latches to give a measure of jitter.
摘要翻译：一种抖动测量电路和方法，具有用于接收其测试抖动的参考信号的输入端，用于接收具有一系列周期的时钟信号的输入端和用于测量参考信号和时钟信号之间的延迟的测量电路在循环周期基础上，给出周期抖动测量的周期。测量电路包括多个n级，每级具有包括输入的延迟元件。第二和稍后的延迟元件的输入连接到前一级的输出，第一延迟元件具有用于接收参考信号的输入。 n个锁存器中的一个连接到对应的一个延迟元件的输入端。每个锁存器具有用于接收时钟信号的时钟输入端，以及当时钟输入由时钟信号的边沿计时时，用于锁存锁存器输入端的值的输出端。提供分析逻辑电路，其具有连接到锁存器的输出的多个n个输入。分析逻辑电路分析锁存器上的值以给出抖动的度量。

5. 发明申请

US20060164067A1 PLL LOOP FILTER CAPACITOR TEST CIRCUIT AND METHOD FOR ON CHIP TESTING OF ANALOG LEAKAGE OF A CIRCUIT 失效
标题翻译： PLL环路滤波电容测试电路及电路模拟泄漏芯片测试方法
公开(公告)号：US20060164067A1
公开(公告)日：2006-07-27
申请号：US11040138
申请日：2005-01-21
申请人： James Eckhardt , Paul Muench , George Smith , Alamgir Tamboli
发明人： James Eckhardt , Paul Muench , George Smith , Alamgir Tamboli
IPC分类号： G01R23/12
CPC分类号： G01R27/02 , G01R31/2639 , G01R31/2884
摘要： A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers. The reference resistor circuit is broken into several series resistors and additional transistors and resistors are supplied with their terminals shorted out, to allow for RIT-B circuit tuning. The output of the test circuit provides the measurement of analog leakage to a digital tester for testing of chips having the circuit during manufacturing test.
摘要翻译：现有设计中的测试电路，使测试电路能够在电路内直接测试。本发明提供了一种在使用现有引脚的简单数字测试仪中测试和测量测试期间PLL环路滤波电容器漏电泄漏的方法。测试PLL电路具有用于测量泄漏的多个电容器和响应放大器电路，包括具有串联耦合的多个晶体管的第一电容器组和耦合到第一放大器的参考电阻器电路和具有串联耦合的多个晶体管的第二电容器组并且所述参考电阻器电路耦合到第二放大器以测量穿过耦合到所述第一和第二放大器的相应电容器的泄漏，并且提供所述泄漏的输出与所述第一和第二放大器的输出进行测量。参考电阻电路分为几个串联电阻，额定的晶体管和电阻的端子短路，以允许RIT-B电路调谐。测试电路的输出提供了对数字测试仪的模拟泄漏测量，用于在制造测试期间测试具有电路的芯片。

6. 发明申请

US20060176080A1 Power supply noise insensitive multiplexer 失效
标题翻译：电源噪声敏感多路复用器
公开(公告)号：US20060176080A1
公开(公告)日：2006-08-10
申请号：US11054831
申请日：2005-02-10
申请人： Michael Sperling , Seongwon Kim , Paul Muench , Hector Saenz
发明人： Michael Sperling , Seongwon Kim , Paul Muench , Hector Saenz
IPC分类号： H03K19/084
CPC分类号： H03K17/693 , H03K17/162
摘要： CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.
摘要翻译：用于在数据输入之间复用的CMOS电路具有对电源噪声的高灵敏度，导致延迟变化。通过利用多路复用器结构中的电流控制逆变器，可以通过两种复用方法之一实现电源不敏感。第一种方法将开关置于数据输入端，而第二种方式将开关置于电流控制逆变器固有的模拟偏置电压上。

7. 发明申请

US20050224586A1 Circuits associated with fusible elements for establishing and detecting of the states of those elements 失效
标题翻译：与可熔元件相关联的电路，用于建立和检测这些元件的状态
公开(公告)号：US20050224586A1
公开(公告)日：2005-10-13
申请号：US10819865
申请日：2004-04-07
申请人： Seth Erlebacher , Paul Muench , George Smith , Gary Steinbrueck
发明人： Seth Erlebacher , Paul Muench , George Smith , Gary Steinbrueck
IPC分类号： G06K19/06 , G06K19/067 , G11C17/18 , H01L23/525 , H01L23/544
CPC分类号： H01L23/544 , G06K19/067 , G11C17/18 , H01L23/5256 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A state detection circuit for a fusible element includes a differential sensing circuit that compares voltage at a detection point in a path containing the fusible element with that at a reference point in a path establishing a non-zero reference voltage. The paths are similarly configured except one contains the fusible element while the other contains a device establishing the reference voltage. The two paths in any given sensing circuit are located in close proximity to each other so that even though element parameters in the paths of different sensing circuits may vary significantly, those values track each other in the given sensing circuit. As a result, the normal non-zero value of the voltage at the reference point maintains a relationship to that at the detection point that enables the differential sensing circuit to detect between a fused and an unfused element irrespective of variation in circuit element parameters. In order to prevent detection circuits and other circuits on the chip being damaged, during blowing of the fusible elements, voltage level of the sensing circuits are chosen to isolate the detection circuits from the other circuits on the semiconductor chip and the excitation levels applied to the detection circuits are raised to maintain differential voltages in the detection circuits at sufficiently low levels to prevent damage.
摘要翻译：用于可熔元件的状态检测电路包括差分感测电路，其将包含可熔元件的路径中的检测点处的电压与建立非零参考电压的路径中的参考点处的电压进行比较。除了一个包含可熔元件，而另一个包含建立参考电压的器件之外，这些路径被类似地配置。任何给定的感测电路中的两条路径彼此靠近，使得尽管不同感测电路的路径中的元件参数可能会显着变化，但是这些值在给定的感测电路中彼此跟踪。结果，参考点处的电压的正常非零值保持与检测点的正常非零值，使得差分感测电路能够检测融合元件和未熔接元件之间，而与电路元件参数的变化无关。为了防止芯片上的检测电路和其他电路被损坏，在吹制可熔元件期间，选择感测电路的电压电平以将检测电路与半导体芯片上的其他电路隔离，并且施加到提高检测电路以将检测电路中的差分电压保持在足够低的水平以防止损坏。

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