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1. 发明授权

US06651232B1 Method and system for progressive clock tree or mesh construction concurrently with physical design 有权
标题翻译：与物理设计同时进行的时钟树或网格构造的方法和系统
公开(公告)号：US06651232B1
公开(公告)日：2003-11-18
申请号：US09186430
申请日：1998-11-05
申请人： Lawrence Pileggi , Christopher Dunn , Satyamurthy Pullela , Majid Sarrafzadeh , Tong Gao , Salil Raje
发明人： Lawrence Pileggi , Christopher Dunn , Satyamurthy Pullela , Majid Sarrafzadeh , Tong Gao , Salil Raje
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F17/5077
摘要： Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.
摘要翻译：逐渐优化的时钟树/网格构建与所有剩余对象的放置同时执行。时钟树/网格被松散地指定用于初始放置，然后是渐进的详细放置。特别地，优选的方法为时钟树/网格构造提供了自动化和可靠的解决方案，与布置过程同时发生，使得时钟树布线和缓冲考虑并影响所有其他对象（诸如逻辑门，存储器元件，宏单元）的布局和布线，因此，以这种并发方式，时钟树/网格预接线和预缓冲可以基于仅使用分区信息（即，在对象放置之前）构建近似时钟树。此外，目前的方法提供了基于改进的基于DME的时钟树拓扑构造而不进行曲折，并且缓冲时钟树构建的递归算法。

2. 发明申请

US20050204315A1 Data structures for representing the logical and physical information of an integrated circuit 有权
标题翻译：用于表示集成电路的逻辑和物理信息的数据结构
公开(公告)号：US20050204315A1
公开(公告)日：2005-09-15
申请号：US10800042
申请日：2004-03-12
申请人： David Knol , Salil Raje
发明人： David Knol , Salil Raje
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock. Net data structures in the physical hierarchy define which nets are connected to which pins. PCellview data structures define the internal structure of each pblock.
摘要翻译：一种用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套的pblock组成的物理层次来创建平面图，以定义在逻辑网表中定义的电路的期望位置。每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。每个pblock数据结构包含指向该plbock的网表上的电路的指针，标识其中嵌套的其他pblock，并且至少包含该pblock的边界引脚列表。物理层次中的网络数据结构定义了哪些网络连接到哪些引脚。 PCellview数据结构定义每个pblock的内部结构。

3. 发明申请

US20050198605A1 System for representing the logical and physical information of an integrated circuit 有权
标题翻译：用于表示集成电路的逻辑和物理信息的系统
公开(公告)号：US20050198605A1
公开(公告)日：2005-09-08
申请号：US10792164
申请日：2004-03-03
申请人： David Knol , Salil Raje
发明人： David Knol , Salil Raje
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.
摘要翻译：一种用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套的pblock组成的物理层次来创建平面图，以定义在逻辑网表中定义的电路的期望位置。每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。每个pblock数据结构包含指向该plbock的网表上的电路的指针，标识嵌套在其中的其他pblock，并包含pblock中的实例的引脚列表。物理层次中的网络数据结构定义了哪些网络连接到哪些引脚。

4. 发明授权

US06523161B1 Method to optimize net lists using simultaneous placement and logic optimization 有权
标题翻译：使用同时放置和逻辑优化优化网络列表的方法
公开(公告)号：US06523161B1
公开(公告)日：2003-02-18
申请号：US09679144
申请日：2000-10-03
申请人： Padmini Gopalakrishnan , Salil Raje
发明人： Padmini Gopalakrishnan , Salil Raje
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： Method to optimize net lists used in the design and fabrication of integrated circuits by using simultaneous placement optimization, logic function optimization and net buffering algorithms. Method simultaneously obtains a placement of logic functions, mapping of logic functions on to library elements and buffering of nets connecting the logic functions.
摘要翻译：通过使用同时布局优化，逻辑功能优化和网络缓冲算法优化集成电路设计和制造中使用的网络列表的方法。方法同时获取逻辑功能的放置，将逻辑功能映射到库元素和缓冲连接逻辑功能的网络。

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