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1. 发明授权

US07917785B2 Method of optimizing performance of multi-core chips and corresponding circuit and computer program product 有权
标题翻译：优化多核芯片性能的方法及相应的电路及计算机程序产品
公开(公告)号：US07917785B2
公开(公告)日：2011-03-29
申请号：US11747300
申请日：2007-05-11
申请人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, Jr.
发明人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, Jr.
IPC分类号： G06F1/26 , G06F1/00 , G06F1/32 , G01R31/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F11/3442 , G06F2201/88 , Y02D10/126 , Y02D10/152 , Y02D10/34
摘要： A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.
摘要翻译：一种优化具有多个核心的多核芯片的性能的方法包括以下步骤：分别确定多个核心中的每一个的Vdd频率SCHMOO特性; 保存表示所述多个核心中的每一个的Vdd频率SCHMOO特性的数据; 基于所保存的数据，配置所述核以获得为给定工作负载提供至少一个最佳功耗和最佳性能的配置; 并且保存配置，使得其可以在周期性和持续性的至少一个上被更新和使用。

2. 发明授权

US07917799B2 Method and system for digital frequency clocking in processor cores 有权
标题翻译：处理器核心数字频率计时方法和系统
公开(公告)号：US07917799B2
公开(公告)日：2011-03-29
申请号：US11734375
申请日：2007-04-12
申请人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, Jr.
发明人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, Jr.
IPC分类号： G06F1/04 , G06F1/12 , G06F1/00 , H03L7/099
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks.
摘要翻译：公开了处理器核心中的数字频率时钟的方法和系统。提供至少一个处理器核心，并且处理器核心具有用于产生输出时钟信号的时钟子系统，其可以是可变频率的模拟信号。数字频率控制数据被发送或分发到处理器核心; 并且一个处理器核心接收发送到核心的数字频率控制数据，并且使用该接收到的数字频率控制数据来设置处理器核心的时钟子系统的输出时钟信号的频率。优选地，多个核被异步计时，并且核心频率被独立设置，并且核心时钟之间没有相位关系。

3. 发明申请

US20080282074A1 METHOD OF OPTIMIZING PERFORMANCE OF MULTI-CORE CHIPS AND CORRESPONDING CIRCUIT AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：优化多芯片和相应电路和计算机程序产品性能的方法
公开(公告)号：US20080282074A1
公开(公告)日：2008-11-13
申请号：US11747300
申请日：2007-05-11
申请人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, JR.
发明人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, JR.
IPC分类号： G06F9/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F11/3442 , G06F2201/88 , Y02D10/126 , Y02D10/152 , Y02D10/34
摘要： A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.
摘要翻译：一种优化具有多个核心的多核芯片的性能的方法包括以下步骤：分别为多个核心中的每一个确定一个Vdd-frequency频率SCHMOO特性; 保存表示所述多个核心中的每一个的Vdd频率SCHMOO特性的数据; 基于所保存的数据，配置所述核以获得为给定工作负载提供至少一个最佳功耗和最佳性能的配置; 并且保存配置，使得可以在周期性和持续性的至少一个上更新和使用配置。

4. 发明授权

US08161314B2 Method and system for analog frequency clocking in processor cores 有权
标题翻译：处理器内核中模拟频率时钟的方法和系统
公开(公告)号：US08161314B2
公开(公告)日：2012-04-17
申请号：US11734334
申请日：2007-04-12
申请人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, Jr.
发明人： Lawrence Jacobowitz , Mark B. Ritter , Daniel J. Stigliani, Jr.
IPC分类号： G06F1/12 , G06F1/00 , G06F1/04
CPC分类号： G06F1/08 , G06F1/06 , H03L7/1976
摘要： A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.
摘要翻译：公开了一种用于处理器核心中频率计时的方法和系统。在该系统中，提供至少一个处理器核心，并且至少一个处理器核心具有用于以可变频率产生模拟输出时钟信号的时钟子系统。数字频率控制数据和模拟信号都传送到该至少一个处理器核心; 并且处理器核心使用接收的模拟信号和数字频率控制数据来设置时钟子系统的输出时钟信号的频率。在优选实施例中，多个核心被异步计时并且核心频率被独立设置。

5. 发明授权

US07945804B2 Methods and systems for digitally controlled multi-frequency clocking of multi-core processors 有权
标题翻译：用于多核处理器数字控制多频时钟的方法和系统
公开(公告)号：US07945804B2
公开(公告)日：2011-05-17
申请号：US11873458
申请日：2007-10-17
申请人： Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
发明人： Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.
摘要翻译：提供了一种用于数字控制的多频时钟的方法和系统。该方法包括在包括多个核的微处理器处接收系统参考振荡器时钟频率。系统参考振荡器时钟频率为本地振荡器提供参考频率。本地振荡器将核心时钟频率提供给至少一个核心。该方法还包括调整本地振荡器以将核心时钟频率以大于系统参考振荡器时钟频率的频率输出，作为与核心或核心相关联的数字频率特性数据的函数。该方法支持对较大系统的可扩展性，并且可以通过核心级别的频率调整来支持增强的电源管理。

6. 发明授权

US07501865B1 Methods and systems for a digital frequency locked loop for multi-frequency clocking of a multi-core processor 有权
标题翻译：用于多核处理器多频时钟的数字锁频环路的方法和系统
公开(公告)号：US07501865B1
公开(公告)日：2009-03-10
申请号：US11873462
申请日：2007-10-17
申请人： Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
发明人： Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/093 , H03L2207/50
摘要： A method and systems for a digital frequency locked loop in a multi-core processor are provided. The method includes applying a dither modulation signal at a dither modulation frequency to modulate an output frequency to provide a clock signal to a core of the multi-core processor. The method further includes filtering a feedback signal of the output frequency with respect to a target frequency. The method additionally includes determining a frequency error in the filtered feedback signal as a function of alignment of the output frequency to the target frequency, and adjusting the output frequency in response to the frequency error.
摘要翻译：提供了一种用于多核处理器中数字频率锁定环路的方法和系统。该方法包括以抖动调制频率应用抖动调制信号来调制输出频率以向多核处理器的核心提供时钟信号。该方法还包括相对于目标频率对输出频率的反馈信号进行滤波。该方法还包括根据输出频率与目标频率的对准确定滤波反馈信号中的频率误差，以及响应于频率误差调整输出频率。

7. 发明授权

US06963119B2 Integrated optical transducer assembly 失效
标题翻译：集成光学换能器组件
公开(公告)号：US06963119B2
公开(公告)日：2005-11-08
申请号：US10250050
申请日：2003-05-30
申请人： Evan G. Colgan , Casimer M. DeCusatis , Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
发明人： Evan G. Colgan , Casimer M. DeCusatis , Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
IPC分类号： H01S5/022 , G02B6/43 , H01L31/0232 , H01S5/02 , H01S5/40 , H01S5/42 , H04B10/12 , H04B10/13 , H04B10/135 , H04B10/14
CPC分类号： H01S5/423 , G02B6/43 , H01L2224/16225 , H01S5/0224 , H01S5/02248 , H01S5/02256
摘要： An integrated optical transducer assembly includes a substrate and an optoelectronic array attached to the substrate. The optoelectronic array further includes a plurality of individual subunits bonded together to form a single array, with each of the subunits including a defined number of individual optoelectronic elements associated therewith. The elastomeric material maintains an original alignment between the plurality of subunits.
摘要翻译：集成光学换能器组件包括衬底和附着到衬底的光电子阵列。光电子阵列还包括多个单独的子单元，其结合在一起以形成单个阵列，其中每个子单元包括与其相关联的限定数量的单个光电元件。弹性体材料保持多个子单元之间的原始对准。

8. 发明授权

US06789957B1 High-density optoelectronic transceiver assembly for optical communication data links 有权
标题翻译：用于光通信数据链路的高密度光电收发器组件
公开(公告)号：US06789957B1
公开(公告)日：2004-09-14
申请号：US10250102
申请日：2003-06-04
申请人： Evan G. Colgan , Casimer M. DeCusatis , Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
发明人： Evan G. Colgan , Casimer M. DeCusatis , Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
IPC分类号： G02B600
CPC分类号： G02B6/43 , G02B6/4206
摘要： An optoelectronic transceiver assembly includes a plurality of optical transmission devices coupled to a first end of a multimode optical fiber core. Each of the plurality of optical transmission devices generates light at a different wavelength with respect to one another. A wavelength demultiplexing device is coupled to a second end of the multimode optical fiber core, and a plurality of optical detection devices is in proximity to the demultiplexing device. The optical detection devices receive light transmitted by the plurality of optical transmission devices.
摘要翻译：光电收发器组件包括耦合到多模光纤芯的第一端的多个光传输装置。多个光传输装置中的每一个相对于彼此产生不同波长的光。波长解复用装置耦合到多模光纤核心的第二端，并且多个光学检测装置靠近解复用装置。光检测装置接收由多个光传输装置发射的光。

9. 发明授权

US07764132B2 All digital frequency-locked loop circuit method for clock generation in multicore microprocessor systems 失效
标题翻译：用于多核微处理器系统中时钟产生的所有数字锁相环电路方法
公开(公告)号：US07764132B2
公开(公告)日：2010-07-27
申请号：US12182204
申请日：2008-07-30
申请人： Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
发明人： Lawrence Jacobowitz , Daniel J. Stigliani, Jr.
IPC分类号： H03K3/03
CPC分类号： H03L7/0996 , H03L7/18
摘要： A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.
摘要翻译：驻留在用于产生具有用于驱动本地核的频率的本地核心时钟的多核微处理器的本地核心上的（DFLL）电路包括被配置为接收核心表征数字数据的微控制器; 环形振荡器，其被配置为产生用于本地核心的本地核心时钟，并且具有设置在环形振荡器的输出和反馈输入之间的延迟链，所述延迟链具有每个接收本地核心时钟的延迟抽头，从而能够在本地核心时钟频率; 以及配置为通过向微控制器生成表示频率的数字信号来连续验证频率的计数器装置，微控制器将本地核心时钟的频率与期望的时钟频率进行比较，并且选择延迟抽头之一基于比较来调整本地核心时钟的频率值。

10. 发明申请

US20090106576A1 METHODS AND SYSTEMS FOR DIGITALLY CONTROLLED MULTI-FREQUENCY CLOCKING OF MULTI-CORE PROCESSORS 有权
标题翻译：数字处理器数字控制多频时钟的方法与系统
公开(公告)号：US20090106576A1
公开(公告)日：2009-04-23
申请号：US11873458
申请日：2007-10-17
申请人： Lawrence Jacobowitz , Daniel J. Stigliani, JR.
发明人： Lawrence Jacobowitz , Daniel J. Stigliani, JR.
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.
摘要翻译：提供了一种用于数字控制的多频时钟的方法和系统。该方法包括在包括多个核的微处理器处接收系统参考振荡器时钟频率。系统参考振荡器时钟频率为本地振荡器提供参考频率。本地振荡器将核心时钟频率提供给至少一个核心。该方法还包括调整本地振荡器以将核心时钟频率以大于系统参考振荡器时钟频率的频率输出，作为与核心或核心相关联的数字频率特性数据的函数。该方法支持对较大系统的可扩展性，并且可以通过核心级别的频率调整来支持增强的电源管理。

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