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1. 发明授权

US06404146B1 Method and system for providing two-dimensional color convergence correction 失效
标题翻译：提供二维色彩会聚校正的方法和系统
公开(公告)号：US06404146B1
公开(公告)日：2002-06-11
申请号：US09773060
申请日：2001-01-31
申请人： Lawrence A. Leske
发明人： Lawrence A. Leske
IPC分类号： G09G128
CPC分类号： G09G1/285 , H04N9/28
摘要： A method and system for providing two-dimensional convergence correction for a color cathode ray tube (CRT) is disclosed. The CRT displays an input video signal comprising a stream of video scan lines which include red, green and blue color signals that are to be displayed on corresponding scan lines and subpixel locations of a display screen. The method and system include storing a plurality of scan lines from the video signal into a buffer. For a particular red, green and blue color signal, horizontal and vertical distortion of the red and blue subpixels in relation to a position of the green subpixel on the display screen are measured. Then, at least one math function is generated that mathematically represents the distortions. Finally, the math functions are applied to control circuitry to control timing of red and blue subpixels read from the frame buffer so that output of the red and blue subpixels are coincident with output of the green subpixel on the display screen.
摘要翻译：公开了一种用于为彩色阴极射线管（CRT）提供二维会聚校正的方法和系统。 CRT显示包括视频扫描线的输入视频信号，该视频扫描线包括要显示在显示屏幕的相应扫描线和子像素位置上的红色，绿色和蓝色信号。该方法和系统包括将多条扫描线从视频信号存储到缓冲器中。对于特定的红色，绿色和蓝色信号，测量相对于显示屏上的绿色子像素的位置的红色和蓝色子像素的水平和垂直失真。然后，产生至少一个数学函数，以数学方式表示失真。最后，将数学函数应用于控制电路，以控制从帧缓冲器读取的红色和蓝色子像素的定时，使得红色和蓝色子像素的输出与显示屏上的绿色子像素的输出一致。

2. 发明申请

US20150333619A1 Enabling nearly constant rate of change of discharge current in an inductor discharging circuit by optimizing a snubber resistor value 审中-公开
标题翻译：通过优化缓冲电阻值，实现电感放电电路中放电电流几乎恒定的变化
公开(公告)号：US20150333619A1
公开(公告)日：2015-11-19
申请号：US14120274
申请日：2014-05-13
申请人： Lawrence A. Leske
发明人： Lawrence A. Leske
IPC分类号： H02M1/34 , G01R27/02
CPC分类号： G01R27/02 , H02M1/34 , H02M2001/348 , H02M2003/1555
摘要： Protecting the switching part of an inductive discharge circuit typically incorporates a power output capacitor and a snubber circuit, incorporating a resistor to dissipate the output coil's stored inductive energy. To effect a nearly constant rate of change of the output inductor's current during the time the snubber circuit is active requires transforming the latter by establishing an optimal snubber resistor value. This invention discloses both a device and method for optimizing a snubber resistor value to enable nearly constant rate of change of discharge current in an inductor discharging circuit.
摘要翻译：保护感应放电电路的开关部分通常包括功率输出电容器和缓冲电路，其包括电阻器以耗散输出线圈所存储的感应能量。为了在缓冲电路处于活动状态期间实现输出电感器电流几乎恒定的变化率，需要通过建立最佳缓冲电阻值来对后者进行变换。本发明公开了一种用于优化缓冲电阻值以使电感放电电路中放电电流变化几乎恒定的装置和方法。

3. 发明授权

US09263965B1 Producing an odd number full wave voltage multiplier 有权
标题翻译：产生奇数全波电压倍增器
公开(公告)号：US09263965B1
公开(公告)日：2016-02-16
申请号：US14545334
申请日：2015-04-22
申请人： Lawrence A. Leske
发明人： Lawrence A. Leske
IPC分类号： H02M7/10
CPC分类号： H02M7/103
摘要： Full wave voltage multipliers mostly provide only even multiples (2×, 4×, 8× . . . ). This invention details a process to produce a full wave multiplier that will provide voltage with an odd numbered multiplicand (3×, 5×, 7×, etc.) from the next-higher-numbered, and thus even-numbered, full wave multiplier (so a 3× will be devised from the 4×, a 5× from the 6×, and for any odd (n)×, from the even (n+1)×). Each of a simplified, base 3× and 5× full wave voltage multiplier are also disclosed.
摘要翻译：全波电压乘法器主要提供偶数倍（2×，4×，8×...）。本发明详细描述了一种产生全波乘法器的过程，该全波乘法器将为下一个较高编号的偶数的全波乘数提供奇数编号的被乘数（3×，5×，7×等）（所以从4×，5×从6×，以及来自偶数（n + 1）×的任何奇数（n）×）将设计3×。还公开了简化的基座3×和5×全波电压倍增器。

4. 发明授权

US07043028B2 Method and system for using an audio transducer as both an input and output device in full duplex operation 有权
公开(公告)号：US07043028B2
公开(公告)日：2006-05-09
申请号：US10029522
申请日：2001-12-21
申请人： Lawrence A. Leske , David L. Medin
发明人： Lawrence A. Leske , David L. Medin
IPC分类号： H04R29/00 , H04R3/00
CPC分类号： H04R3/00
摘要： A method and system for using an audio transducer as both an input device and an output device is disclosed. The method and system include digitally modulating a primary input signal for driving the transducer as an output device, sampling an output signal generated from the transducer during off times of the modulated signal, and determining an input signal from the sampled output signal.

5. 发明授权

US5473385A Clock correction in a video data decoder using video synchronization signals 失效
标题翻译：使用视频同步信号的视频数据解码器中的时钟校正
公开(公告)号：US5473385A
公开(公告)日：1995-12-05
申请号：US254992
申请日：1994-06-07
申请人： Lawrence A. Leske
发明人： Lawrence A. Leske
IPC分类号： H04N5/44 , H04N5/45 , H04N21/43 , H04N21/434 , H04N5/04
CPC分类号： H04N21/4305 , H04N5/4401 , H04N5/45 , H04N21/4341
摘要： In a system which encodes video data in response to an encoding clock, transmits the encoded video data with an encoder clock signal representing the encoding clock frequency, and decodes the video data in response to a decoding clock, system clock accuracy is maintained by adjusting the decoding clock frequency. In order to reduce buffer requirements and to prevent deterioration of video program presentation, the decoding clock frequency is adjusted by slewing only during composite video synchronization periods when composite video decoded from the encoded video stream is not being presented. The preferred video synchronization periods are the vertical blanking interval and the front porch period. Restriction of decoding clock rate adjustment to these periods ensures that decoding clock slew rate limits may be unrestricted, thereby avoiding noticeable effects in the video program presentations.
摘要翻译：在响应于编码时钟编码视频数据的系统中，利用表示编码时钟频率的编码器时钟信号发送编码视频数据，并且响应于解码时钟解码视频数据，通过调整系统时钟精度来维持系统时钟精度解码时钟频率。为了减少缓冲器要求并防止视频节目呈现的恶化，解码时钟频率仅在复合视频同步期间通过回转进行调整，当从编码视频流解码复合视频时不被呈现。优选的视频同步周期是垂直消隐间隔和前沿周期。解码时钟速率调整到这些周期的限制确保解码时钟转换速率限制可能不受限制，从而避免视频节目演示中的显着影响。

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