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1. 发明授权

US10754401B2 Reconfigurable and scalable hardware management architecture 有权
公开(公告)号：US10754401B2
公开(公告)日：2020-08-25
申请号：US16417586
申请日：2019-05-20
申请人： Lattice Semiconductor Corporation
发明人： Srirama Chandra , Robert Bartel
IPC分类号： G06F1/26 , G06F1/20 , G06F1/24 , G06F1/28
摘要： In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.

2. 发明申请

US20160011878A1 System-Level Dual-Boot Capability in Systems Having One or More Devices Without Native Dual-Boot Capability 有权
标题翻译：具有一个或多个没有本机双引导能力的设备的系统的系统级双引导功能
公开(公告)号：US20160011878A1
公开(公告)日：2016-01-14
申请号：US14327811
申请日：2014-07-10
申请人： Lattice Semiconductor Corporation
发明人： Srirama Chandra , Cleo Mui , Cheng Jen Gwo , Saurabh Chedda
IPC分类号： G06F9/44 , G06F12/06 , G06F12/02
CPC分类号： G06F9/4401 , G06F11/00 , G06F11/1417 , G06F12/0246 , G06F12/0638 , G06F2212/1024 , G06F2212/205 , G06F2212/7208
摘要： In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.
摘要翻译：在一个实施例中，系统具有具有本地双引导能力的主可编程设备（PD）和不具有本机双引导能力的一个或多个从属PD。主金色图像包括嵌入式双引导功能。在上电期间，每个PD将其主映像复制到其易失性配置存储器中，并确定主映像是否有效。当主机配置引擎检测到无效的主主映像时，主机的本地双引导功能使主机能够实现系统重启过程，其中包括将主黄金映像从外部存储器设备复制到主控易失性配置存储器中，启动嵌入式双引导功能，从而在启用其他主金色图像功能之前，将从属金色图像从外部存储器件复制到从属的易失性配置存储器中。在不使用本地双引导功能为每个PD提供配置的情况下，实现了显着的系统可靠性和鲁棒性。

3. 发明申请

US20210081577A1 ASSET MANAGEMENT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
公开(公告)号：US20210081577A1
公开(公告)日：2021-03-18
申请号：US17093576
申请日：2020-11-09
申请人： Lattice Semiconductor Corporation
发明人： Fulong Zhang , Srirama Chandra , Sreepada Hegade , Joel Coplen , Wei Han , Yu Sun
IPC分类号： G06F21/76 , G06F9/445 , G06F8/65 , H04L9/32 , G06F21/44
摘要： Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.

4. 发明授权

US09819174B2 Hotswap operations for programmable logic devices 有权
公开(公告)号：US09819174B2
公开(公告)日：2017-11-14
申请号：US14609181
申请日：2015-01-29
申请人： Lattice Semiconductor Corporation
发明人： Christopher W. Dix , Cleo Mui , Cheng-Jen Gwo , Joel Coplen , Srirama Chandra
IPC分类号： H02H9/02 , H02H9/00
CPC分类号： H02H9/004
摘要： Techniques are provided to control hotswap operations with programmable logic devices (PLDs). In particular, a MOSFET is provided to limit an in-rush current drawn from a power supply by capacitive components of an electronic assembly when it is plugged into the live, power supply. A controller with an algorithm is provided to control the MOSFET based on the in-rush current detected at the MOSFET. As such, a feedback control loop is established to selectively bias the gate of the MOSFET based on the detected in-rush current. The algorithm may limit the in-rush current based on a Safe Operating Area (SOA) of the MOSFET. The hotswap process may include multiple phases each with a voltage and/or current limit modeling the voltages and currents of the SOA. The algorithm may transition through the phases with the respective current and/or voltage limits during the hotswap process.

5. 发明授权

US11971992B2 Failure characterization systems and methods for erasing and debugging programmable logic devices 有权
公开(公告)号：US11971992B2
公开(公告)日：2024-04-30
申请号：US17093578
申请日：2020-11-09
申请人： Lattice Semiconductor Corporation
发明人： Fulong Zhang , Srirama Chandra , Sreepada Hegade , Joel Coplen , Wei Han , Yu Sun
IPC分类号： G06F21/57 , G06F8/65 , G06F9/445 , G06F11/36 , G06F12/02 , G06F21/31 , G06F21/44 , G06F21/76 , G06F21/79 , G06F21/85 , H03K19/17768 , H04L9/08 , H04L9/30 , H04L9/32 , G06F21/10
CPC分类号： G06F21/575 , G06F8/65 , G06F9/44505 , G06F11/3656 , G06F12/0246 , G06F21/31 , G06F21/44 , G06F21/572 , G06F21/577 , G06F21/76 , G06F21/79 , G06F21/85 , H03K19/17768 , H04L9/0825 , H04L9/085 , H04L9/0877 , H04L9/30 , H04L9/3236 , H04L9/3252 , G06F21/107 , H04L2209/12
摘要： Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.

6. 发明授权

US09772856B2 System-level dual-boot capability in systems having one or more devices without native dual-boot capability 有权
公开(公告)号：US09772856B2
公开(公告)日：2017-09-26
申请号：US14327811
申请日：2014-07-10
申请人： Lattice Semiconductor Corporation
发明人： Srirama Chandra , Cleo Mui , Cheng Jen Gwo , Saurabh Chheda
IPC分类号： G06F9/44 , G06F12/02 , G06F12/06 , G06F11/00 , G06F11/14
CPC分类号： G06F9/4401 , G06F11/00 , G06F11/1417 , G06F12/0246 , G06F12/0638 , G06F2212/1024 , G06F2212/205 , G06F2212/7208
摘要： In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.

7. 发明公开

US20240232439A1 TAMPER DETECTION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 审中-公开
公开(公告)号：US20240232439A1
公开(公告)日：2024-07-11
申请号：US18584894
申请日：2024-02-22
申请人： Lattice Semiconductor Corporation
发明人： Fulong Zhang , Yu Sun , Srirama Chandra , Sreepada Hegade , Joel Coplen , Wei Han , Warren Juenemann
IPC分类号： G06F21/70
CPC分类号： G06F21/70
摘要： Systems and methods for asset tamper detection management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to detect an asset tamper attempt on a targeted asset of the secure PLD, and to lock a securable asset associated with the detected asset tamper attempt, where the securable asset includes the targeted asset, the configuration I/O, and/or a communication bus of the secure PLD.

8. 发明申请

US20210083675A1 KEY PROVISIONING SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
公开(公告)号：US20210083675A1
公开(公告)日：2021-03-18
申请号：US17093572
申请日：2020-11-09
申请人： Lattice Semiconductor Corporation
发明人： Srirama Chandra , Fulong Zhang , Sreepada Hegade , Joel Coplen , Wei Han , Yu Sun
IPC分类号： H03K19/17768 , H04L9/08
摘要： Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.

9. 发明申请

US20210081578A1 FAILURE CHARACTERIZATION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
公开(公告)号：US20210081578A1
公开(公告)日：2021-03-18
申请号：US17093578
申请日：2020-11-09
申请人： Lattice Semiconductor Corporation
发明人： Fulong Zhang , Srirama Chandra , Sreepada Hegade , Joel Coplen , Wei Han , Yu Sun
IPC分类号： G06F21/85 , G06F21/79 , G06F21/57 , G06F21/31 , G06F12/02 , G06F11/36
摘要： Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.

10. 发明申请

US20210081536A1 SECURE BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
公开(公告)号：US20210081536A1
公开(公告)日：2021-03-18
申请号：US17093582
申请日：2020-11-09
申请人： Lattice Semiconductor Corporation
发明人： Fulong Zhang , Srirama Chandra , Sreepada Hegade , Joel Coplen , Wei Han , Yu Sun
IPC分类号： G06F21/57 , G06F21/76 , H04L9/32 , H04L9/30
摘要： Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.

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