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1. 发明申请

US20120194221A1 ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS 有权
标题翻译：用于记忆细胞感测的高级转换器和方法
公开(公告)号：US20120194221A1
公开(公告)日：2012-08-02
申请号：US13019873
申请日：2011-02-02
申请人： Larry J. Koudele , Robert B. Eisenhuth
发明人： Larry J. Koudele , Robert B. Eisenhuth
IPC分类号： H03K5/19
CPC分类号： H04L7/0331 , G04F10/005 , G06F11/0793 , G11C11/4076 , G11C11/5642 , G11C29/02 , G11C29/12015 , G11C2211/5644 , H03M1/207 , H03M1/54
摘要： A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
摘要翻译：计数器配置与延迟配置协同工作，使得计数器配置基于给定的时钟速度和给定的时钟间隔对输入间隔进行计数，而延迟配置提供的增强数据输出大于由给定时钟速度。计数器配置响应于时钟间隔中的选定边沿计数。校正装置和相关方法形式的装置被配置为至少监视延迟配置输出，用于检测输入间隔的端点与给定时钟信号中所选择的时钟沿的最近出现之间的特定时间关系这表明增强数据输出中至少存在潜在的错误，并且确定潜在误差是否是后续用于校正增强数据输出的实际误差。

2. 发明授权

US08522087B2 Advanced converters for memory cell sensing and methods 有权
标题翻译：用于存储单元感测和方法的高级转换器
公开(公告)号：US08522087B2
公开(公告)日：2013-08-27
申请号：US13019873
申请日：2011-02-02
申请人： Larry J. Koudele , Robert B. Eisenhuth
发明人： Larry J. Koudele , Robert B. Eisenhuth
IPC分类号： G06K5/04
CPC分类号： H04L7/0331 , G04F10/005 , G06F11/0793 , G11C11/4076 , G11C11/5642 , G11C29/02 , G11C29/12015 , G11C2211/5644 , H03M1/207 , H03M1/54
摘要： A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
摘要翻译：计数器配置与延迟配置协同工作，使得计数器配置基于给定的时钟速度和给定的时钟间隔对输入间隔进行计数，而延迟配置提供的增强数据输出大于由给定时钟速度。计数器配置响应于时钟间隔中的选定边沿计数。校正装置和相关方法形式的装置被配置为至少监视延迟配置输出，用于检测输入间隔的端点与给定时钟信号中所选择的时钟沿的最近出现之间的特定时间关系这表明增强数据输出中至少存在潜在的错误，并且确定潜在误差是否是后续用于校正增强数据输出的实际误差。

3. 发明授权

US5436887A Digital full-duplex transceiver 失效
标题翻译：数字全双工收发器
公开(公告)号：US5436887A
公开(公告)日：1995-07-25
申请号：US10773
申请日：1993-01-29
申请人： Robert B. Eisenhuth
发明人： Robert B. Eisenhuth
IPC分类号： G06F13/40 , H04B1/58 , H04L5/14 , H04L25/02 , H04B1/52
CPC分类号： H04L25/028 , G06F13/4072 , H04B1/58 , H04L5/1423 , H04L25/0294
摘要： The present invention provides a digital full-duplex line driver which allows digital information to be transmitted across a single bus simultaneously in both directions. The present invention accomplishes this by using both the voltage level on the bus and the current flowing through either a driver on one side of the bus or through the bus itself to decode the required information.
摘要翻译：本发明提供一种数字全双工线路驱动器，其允许在两个方向上同时在单个总线上传输数字信息。本发明通过使用总线上的电压电平和流过总线一侧的驱动器或通过总线本身的电流来解码所需的信息来实现这一点。

4. 发明申请

US20220029640A1 Advanced Bitwise Operations and Apparatus in a Multi-Level System with Nonvolatile Memory 有权
公开(公告)号：US20220029640A1
公开(公告)日：2022-01-27
申请号：US16939004
申请日：2020-07-26
申请人： Robert B. Eisenhuth , Stephen P. Van Aken
发明人： Robert B. Eisenhuth , Stephen P. Van Aken
IPC分类号： H03M13/25 , G06F3/06 , G06F11/10 , H03M13/15
摘要： A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

5. 发明授权

US09064575B2 Determining whether a memory cell state is in a valley between adjacent data states 有权
标题翻译：确定存储单元状态是否处于相邻数据状态之间的谷
公开(公告)号：US09064575B2
公开(公告)日：2015-06-23
申请号：US13566180
申请日：2012-08-03
申请人： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak , Robert B. Eisenhuth
发明人： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak , Robert B. Eisenhuth
IPC分类号： G11C16/34 , G11C16/04 , G11C16/06 , G11C11/56 , G11C16/26 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C29/52
摘要： The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.
摘要翻译：本公开包括与相邻数据状态之间的谷中的存储器单元状态有关的装置和方法。多种方法可以包括确定存储器单元的状态是否处于与相应数据状态相关联的状态的相邻分布之间的谷内。该方法还可以包括发送指示存储器单元的数据状态的信号以及存储单元的状态是否在谷中。

6. 发明申请

US20090241006A1 Bitwise Operations and Apparatus in a Multi-Level System 有权
标题翻译：多级系统中的按位操作和装置
公开(公告)号：US20090241006A1
公开(公告)日：2009-09-24
申请号：US12403546
申请日：2009-03-13
申请人： Bruce A. Liikanen , Stephen P. Van Aken , Gerald L. Cadloni , John L. Seabury , Robert B. Eisenhuth
发明人： Bruce A. Liikanen , Stephen P. Van Aken , Gerald L. Cadloni , John L. Seabury , Robert B. Eisenhuth
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0041 , G06F11/1072 , H03M13/253 , H03M13/2936 , H03M13/353 , H04L63/0428
摘要： A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
摘要翻译：系统使用多级编码，其中多个符号的每个符号表示用于使用多级传输信道传送的用户数据符号流中的多于一位的信息。以数字逐位形式表示用户数据符号，使得每个符号被呈现为多个位，并且每个位受到不同的误差概率。基于与多个中的每个位相关联的不同误差概率应用纠错过程。通道可被配置为支持马赛克瓦片结构，每个瓦片包含通道符号，使得所选择的瓦片具有与其他瓦片不同的集体误差概率。可以将定制编码应用于瓦片结构，以基于总体可用校正功率将所选量的误差校正功率分配给所选择的瓦片。

7. 发明申请

US20140036589A1 MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES 有权
标题翻译：在相邻数据状态之间的谷中的存储单元状态
公开(公告)号：US20140036589A1
公开(公告)日：2014-02-06
申请号：US13566180
申请日：2012-08-03
申请人： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak , Robert B. Eisenhuth
发明人： Sivagnanam Parthasarathy , Patrick R. Khayat , Mustafa N. Kaynak , Robert B. Eisenhuth
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C29/52
摘要： The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.
摘要翻译：本公开包括与相邻数据状态之间的谷中的存储器单元状态有关的装置和方法。多种方法可以包括确定存储器单元的状态是否处于与相应数据状态相关联的状态的相邻分布之间的谷内。该方法还可以包括发送指示存储器单元的数据状态的信号以及存储单元的状态是否在谷中。

8. 发明申请

US20110302475A1 Advanced Bitwise Operations and Apparatus in a Multi-Level System with Nonvolatile Memory 有权
标题翻译：具有非易失性存储器的多级系统中的高级按位操作和装置
公开(公告)号：US20110302475A1
公开(公告)日：2011-12-08
申请号：US12794706
申请日：2010-06-04
申请人： Robert B. Eisenhuth , Sephen P. Van Aken
发明人： Robert B. Eisenhuth , Sephen P. Van Aken
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/1012 , G06F11/10 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/353 , H03M13/356 , H03M13/6362
摘要： A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.
摘要翻译：数字系统，组件和方法被配置有非易失性存储器，用于使用码字存储数字数据。数据存储在存储器中，每个存储器的每个存储单元使用多个位。基于输入参数，可以在代码字到码字的基础上改变与存储器有关的写入操作和读取操作的代码效率。代码效率可以根据改变任何一个输入参数而改变，包括由存储器存储的位密度。描述存储和读取分数位密度。

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