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    • 6. 发明授权
    • Globally observing load operations prior to fence instruction and post-serialization modes
    • 在栅栏指令和后序列化模式之前,全局观察加载操作
    • US07249245B2
    • 2007-07-24
    • US10778512
    • 2004-02-12
    • Lance E. HackingDebbie Marr
    • Lance E. HackingDebbie Marr
    • G06F9/312
    • G06F9/30087G06F9/3836G06F9/384G06F9/3857
    • A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed. The processor further may include a control register having a first mode storage to store a mode control selection for pre-serialization and a second mode storage to store a mode control selection for post-serialization to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction. Other embodiments are described and claimed.
    • 一种系统包括存储器单元和处理器,其中处理器具有负载缓冲器以存储第一指令和高速缓存控制器,以将第一指令阻止到高速缓存控制器的调度中,直到在从第一指令取出第一指令之前的加载操作的加载数据 全局观察记忆单元。 处理器还可以包括具有第一模式存储器的控制寄存器,用于存储用于预序列化的模式控制选择,以及存储用于后序列化的模式控制选择的第二模式存储,以使得能够控制前序列化和后序列化 相对于第一条指令的加载操作。 描述和要求保护其他实施例。