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1. 发明申请

US20160118296A1 Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition 有权
标题翻译：使用选择性阻挡沉积的层间导体预填充
公开(公告)号：US20160118296A1
公开(公告)日：2016-04-28
申请号：US14874307
申请日：2015-10-02
申请人： Lam Research Corporation
发明人： Artur Kolics , William T. Lee , Larry Zhao , Derek Wong , Praveen Nalla , Kaihan Ashtiani , Patrick A. Van Cleemput , Yezdi Dordi
IPC分类号： H01L21/768 , H01L21/02 , H01L23/532 , H01L21/288
CPC分类号： H01L23/53238 , C23C16/26 , H01L21/02063 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/288 , H01L21/2885 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
摘要翻译：提供了一种衬底，其具有形成在衬底上的电介质材料内的双镶嵌结构。双镶嵌结构包括沟槽和形成为从沟槽的底部延伸到下面的导电材料的开口，其中下面的导电材料暴露在开口的底部。双镶嵌结构暴露于密封过程中，开口中的介电材料的暴露表面被密封，而不覆盖暴露在开口底部的下面的导电材料。密封过程可以是可流动膜的沉积，无定形碳阻挡层的沉积和氨基的自组装单层的形成中的一种或多种。在密封过程之后，执行无电镀沉积工艺，以直到顶部的方式从底部到顶部的方式用金属材料填充开口。

2. 发明授权

US09583386B2 Interlevel conductor pre-fill utilizing selective barrier deposition 有权
标题翻译：使用选择性阻隔沉积的层间导体预填充
公开(公告)号：US09583386B2
公开(公告)日：2017-02-28
申请号：US14874307
申请日：2015-10-02
申请人： Lam Research Corporation
发明人： Artur Kolics , William T. Lee , Larry Zhao , Derek Wong , Praveen Nalla , Kaihan Ashtiani , Patrick A. Van Cleemput , Yezdi Dordi
IPC分类号： H01L21/768 , H01L23/532 , C23C16/26
CPC分类号： H01L23/53238 , C23C16/26 , H01L21/02063 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/288 , H01L21/2885 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
摘要翻译：提供了一种衬底，其具有形成在衬底上的电介质材料内的双镶嵌结构。双镶嵌结构包括沟槽和形成为从沟槽的底部延伸到下面的导电材料的开口，其中下面的导电材料暴露在开口的底部。双镶嵌结构暴露于密封过程中，开口中的介电材料的暴露表面被密封，而不覆盖暴露在开口底部的下面的导电材料。密封过程可以是可流动膜的沉积，无定形碳阻挡层的沉积和氨基的自组装单层的形成中的一种或多种。在密封过程之后，执行无电镀沉积工艺，以直到顶部的方式从底部到顶部的方式用金属材料填充开口。

3. 发明授权

US09287183B1 Using electroless deposition as a metrology tool to highlight contamination, residue, and incomplete via etch 有权
标题翻译：使用无电沉积作为计量工具来突出污染，残留和不完全通过蚀刻
公开(公告)号：US09287183B1
公开(公告)日：2016-03-15
申请号：US14675350
申请日：2015-03-31
申请人： Lam Research Corporation
发明人： Larry Zhao , Artur Kolics , Praveen Nalla
IPC分类号： H01L21/66 , H01L21/02 , H01L21/768
CPC分类号： H01L22/12 , H01L21/0206 , H01L21/02063 , H01L21/02068 , H01L21/288 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76879 , H01L22/24
摘要： A method for detecting contamination on a patterned substrate includes: performing a via etch operation on a substrate, wherein the via etch operation is configured to define a via feature on the substrate and expose an etch-stop layer at a bottom of the via feature; performing an etch-stop removal operation on the substrate, wherein the etch-stop removal operation is configured for removing the etch-stop layer at the bottom of the via feature to expose a metallic feature underlying the etch-stop layer; applying an electroless deposition solution to the substrate, the applied electroless deposition solution configured for selectively depositing a metallic material over the exposed metallic feature and on metallic contaminants on exposed surfaces of the substrate, the metallic contaminants being generated from the metallic feature during the etch-stop removal operation; performing an inspection operation on the substrate to identify the metallic contaminants that have been deposited with the metallic material.
摘要翻译：用于检测图案化衬底上的污染物的方法包括：对衬底执行通孔蚀刻操作，其中通孔蚀刻操作被配置为在衬底上限定通孔特征并且在通孔特征的底部露出蚀刻停止层; 在所述衬底上执行蚀刻停止去除操作，其中所述蚀刻停止去除操作被配置为去除所述通孔特征底部的所述蚀刻停止层以暴露所述蚀刻停止层下面的金属特征; 将无电沉积溶液施加到所述基底上，所施加的无电沉积溶液被配置为在所述暴露的金属特征上选择性地沉积金属材料和所述基底的暴露表面上的金属污染物，所述金属污染物在所述蚀刻期间由所述金属特征产生，停止清除操作; 对基板执行检查操作以识别已经用金属材料沉积的金属污染物。

4. 发明授权

US10262943B2 Interlevel conductor pre-fill utilizing selective barrier deposition 有权
公开(公告)号：US10262943B2
公开(公告)日：2019-04-16
申请号：US15877751
申请日：2018-01-23
申请人： Lam Research Corporation
发明人： Artur Kolics , William T. Lee , Larry Zhao , Derek Wong , Praveen Nalla , Kaihan Ashtiani , Patrick A. Van Cleemput , Yezdi Dordi
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L23/532 , H01L21/02 , H01L21/285 , H01L21/288 , C23C16/26
摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

5. 发明申请

US20180151503A1 Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition 审中-公开
公开(公告)号：US20180151503A1
公开(公告)日：2018-05-31
申请号：US15877751
申请日：2018-01-23
申请人： Lam Research Corporation
发明人： Artur Kolics , William T. Lee , Larry Zhao , Derek Wong , Praveen Nalla , Kaihan Ashtiani , Patrick A. Van Cleemput , Yezdi Dordi
IPC分类号： H01L23/532 , H01L21/768 , H01L21/288 , H01L23/528 , H01L21/285 , H01L23/522 , H01L21/02
CPC分类号： H01L23/53238 , C23C16/26 , H01L21/02063 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/288 , H01L21/2885 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

6. 发明授权

US09875968B2 Interlevel conductor pre-fill utilizing selective barrier deposition 有权
公开(公告)号：US09875968B2
公开(公告)日：2018-01-23
申请号：US15442307
申请日：2017-02-24
申请人： Lam Research Corporation
发明人： Artur Kolics , William T. Lee , Larry Zhao , Derek Wong , Praveen Nalla , Kaihan Ashtiani , Patrick A. Van Cleemput , Yezdi Dordi
IPC分类号： H01L21/768 , H01L23/532 , H01L21/285 , H01L21/02 , H01L21/288 , H01L23/528 , H01L23/522
CPC分类号： H01L23/53238 , C23C16/26 , H01L21/02063 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/288 , H01L21/2885 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

7. 发明申请

US20170162512A1 Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition 审中-公开
公开(公告)号：US20170162512A1
公开(公告)日：2017-06-08
申请号：US15442307
申请日：2017-02-24
申请人： Lam Research Corporation
发明人： Artur Kolics , William T. Lee , Larry Zhao , Derek Wong , Praveen Nalla , Kaihan Ashtiani , Patrick A. Van Cleemput , Yezdi Dordi
IPC分类号： H01L23/532 , H01L21/02 , H01L23/522 , H01L23/528 , H01L21/285 , H01L21/768 , H01L21/288
CPC分类号： H01L23/53238 , C23C16/26 , H01L21/02063 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/288 , H01L21/2885 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

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