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    • 3. 发明授权
    • Method and apparatus for performing selective encryption/decryption in a data storage system
    • 用于在数据存储系统中执行选择性加密/解密的方法和装置
    • US08892905B2
    • 2014-11-18
    • US11726428
    • 2007-03-21
    • Adam Y. LeeVarun MalhotraDaniel ManHung WongTirthankar LahiriKiran GoyalJuan R. LoaizaPaul Youn
    • Adam Y. LeeVarun MalhotraDaniel ManHung WongTirthankar LahiriKiran GoyalJuan R. LoaizaPaul Youn
    • G06Q30/02H04L9/08
    • H04L9/0894
    • One embodiment of the present invention provides a system for performing selective encryption/decryption in a data storage system. During operation, the system receives a data block from a storage medium at an input/output layer, wherein the input/output layer serves as an interface between the storage medium and a buffer cache. Next, the system determines whether the data block is an encrypted data block. If not, the system stores the data block in the buffer cache. Otherwise, if the data block is an encrypted data block, the system retrieves a storage-key, wherein the storage-key is associated with a subset of storage, which is associated with the encrypted data block. Using the storage-key, the system then decrypts the encrypted data block to produce a decrypted data block. Finally, the system stores the decrypted data block in the buffer cache, wherein the data block remains encrypted in the storage medium.
    • 本发明的一个实施例提供一种用于在数据存储系统中执行选择性加密/解密的系统。 在操作期间,系统在输入/输出层从存储介质接收数据块,其中输入/输出层用作存储介质和缓冲器高速缓存之间的接口。 接下来,系统确定数据块是否是加密数据块。 如果没有,系统将数据块存储在缓冲区高速缓存中。 否则,如果数据块是加密数据块,则系统检索存储密钥,其中存储密钥与与加密数据块相关联的存储子集相关联。 使用存储密钥,系统然后解密加密的数据块以产生解密的数据块。 最后,系统将解密的数据块存储在缓冲器高速缓存中,其中数据块在存储介质中保持加密。
    • 6. 发明授权
    • System and method for predicting cache performance
    • 用于预测缓存性能的系统和方法
    • US06952664B1
    • 2005-10-04
    • US09834342
    • 2001-04-13
    • Tirthankar LahiriJuan R. LoaizaArvind NithrakashyapWilliam H. Bridge
    • Tirthankar LahiriJuan R. LoaizaArvind NithrakashyapWilliam H. Bridge
    • G06F17/50G06G17/50
    • G06F17/5022
    • A system and methods for simulating the performance (e.g., miss rate) of one or more caches. A cache simulator comprises a segmented list of buffers, with each buffer configured to store a data identifier and an identifier of the buffer's segment. Data references, which may be copied from an operational cache, are applied to the list to conduct the simulation. Initial estimates of each cache's miss rate include the number of references that missed all segments of the list plus the hits in all segments not part of the cache. A correction factor is generated from the ratio of actual misses incurred by the operational cache to the estimated misses for a simulated cache of the same size as the operational cache. Final predictions are generated by multiplying the initial estimates by the correction factor. The size of the operational cache may be dynamically adjusted based on the final predictions.
    • 用于模拟一个或多个高速缓存的性能(例如,错过率)的系统和方法。 缓存模拟器包括分段缓冲器列表,其中每个缓冲器被配置为存储数据标识符和缓冲器段的标识符。 可以从操作缓存复制的数据引用被应用于列表以进行模拟。 每个缓存的未命中率的初始估计包括丢失列表的所有段的引用数量加上不是高速缓存的一部分的所有段中的命中。 由操作缓存引起的实际未命中率与与操作缓存大小相同的模拟高速缓存的估计未命中的比率产生校正因子。 最终预测是通过将初始估计乘以校正因子而产生的。 可以基于最终预测来动态地调整操作高速缓存的大小。