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1. 发明授权

US08996969B2 Low density parity check decoder with miscorrection handling 有权
标题翻译：低密度奇偶校验解码器与错误处理
公开(公告)号：US08996969B2
公开(公告)日：2015-03-31
申请号：US13708941
申请日：2012-12-08
申请人： LSI Corporation
发明人： Anatoli A. Bolotov , Shaohua Yang , Zongwang Li , Mikhail I Grinchuk , Lav D. Ivanovic , Fan Zhang , Yang Han
IPC分类号： H03M13/00 , H03M13/13 , H03M13/11
CPC分类号： H03M13/13 , H03M13/1111 , H03M13/1142
摘要： A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.
摘要翻译：数据处理系统包括解码器电路，校正子计算电路和散列计算电路。解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。散列计算电路可操作以基于复合矩阵的第二部分来计算散列。当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

2. 发明授权

US08797668B1 Systems and methods for penalty based multi-variant encoding 有权
标题翻译：基于惩罚的多变量编码的系统和方法
公开(公告)号：US08797668B1
公开(公告)日：2014-08-05
申请号：US13875951
申请日：2013-05-02
申请人： LSI Corporation
发明人： Mikhail I Grinchuk , Anatoli A. Bolotov , Shaohua Yang , Victor Krachkovsky , Zongwang Li
IPC分类号： G11B5/02 , G11B5/09 , H04H9/00
CPC分类号： H03M13/611 , G11B5/09 , G11B2020/185 , H03M13/1102 , H03M13/1515 , H03M13/353 , H03M13/3738
摘要： Systems, methods, devices, circuits for data processing, and more particularly to penalty based multi-variant encoding of data.
摘要翻译：用于数据处理的系统，方法，设备，电路，更具体地涉及数据的基于惩罚的多变量编码。

3. 发明申请

US20140325303A1 Systems and Methods for Protected Data Encoding 审中-公开
标题翻译：保护数据编码的系统和方法
公开(公告)号：US20140325303A1
公开(公告)日：2014-10-30
申请号：US13875357
申请日：2013-05-02
申请人： LSI CORPORATION
发明人： Shaohua Yang , Anatoli A. Bolotov , Mikhail I. Grinchuk
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G11B20/1833 , H03M13/116 , H03M13/31 , H03M13/611 , H03M13/6343
摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for encoding data sets.
摘要翻译：本发明涉及用于数据处理的系统和方法，更具体地涉及用于编码数据集的系统和方法。

4. 发明申请

US20140168811A1 Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling 有权
标题翻译：具有低综合征错误处理的不规则低密度奇偶校验解码器
公开(公告)号：US20140168811A1
公开(公告)日：2014-06-19
申请号：US13777381
申请日：2013-02-26
申请人： LSI CORPORATION
发明人： Shaohua Yang , Anatoli A. Bolotov , Chung-Li Wang , Zongwang Li , Shu Li , Mikhail I. Grinchuk
IPC分类号： H03M13/13 , G11B20/18
CPC分类号： G11B20/18 , G11B20/1833 , G11B2020/185 , H03M13/09 , H03M13/1111 , H03M13/1128 , H03M13/27 , H03M13/6331
摘要： A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.
摘要翻译：公开了一种数据处理系统，包括数据解码器电路，错误处理电路和综合检查电路。数据解码器电路可操作以将数据解码算法应用于解码器输入以产生解码输出，并计算指示解码输出的误差电平的校正子。错误处理电路可操作以确定解码输出中的任何错误是否涉及用户数据位。综合征检查器电路可操作以至少部分地基于综合征来触发误差处理电路。

5. 发明申请

US20140289582A1 Systems and Methods for Reduced Constraint Code Data Processing 有权
标题翻译：减少约束代码数据处理的系统和方法
公开(公告)号：US20140289582A1
公开(公告)日：2014-09-25
申请号：US13853711
申请日：2013-03-29
申请人： LSI CORPORATION
发明人： Shu Li , Anatoli A. Bolotov , Shaohua Yang , Fan Zhang
IPC分类号： H03M13/11
CPC分类号： H03M13/116 , G11B20/1833 , H03M13/1111 , H03M13/1171 , H03M13/2957 , H03M13/6325 , H03M13/6343
摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
摘要翻译：本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法。

6. 发明申请

US20140164866A1 Low Density Parity Check Decoder With Miscorrection Handling 有权
标题翻译：低密度奇偶校验解码器与误码处理
公开(公告)号：US20140164866A1
公开(公告)日：2014-06-12
申请号：US13708941
申请日：2012-12-08
申请人： LSI CORPORATION
发明人： Anatoli A. Bolotov , Shaohua Yang , Zongwang Li , Mikhail I. Grinchuk , Lav D. Ivanovic , Fan Zhang , Yang Han
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/1111 , H03M13/1142
摘要： A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.
摘要翻译：公开了一种数据处理系统，包括解码器电路，校正子计算电路和散列计算电路。解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。散列计算电路可操作以基于复合矩阵的第二部分来计算散列。当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

7. 发明授权

US09281843B2 Systems and methods for reduced constraint code data processing 有权
标题翻译：用于减少约束代码数据处理的系统和方法
公开(公告)号：US09281843B2
公开(公告)日：2016-03-08
申请号：US13853711
申请日：2013-03-29
申请人： LSI Corporation
发明人： Shu Li , Anatoli A. Bolotov , Shaohua Yang , Fan Zhang
IPC分类号： H03M13/11 , H03M13/29 , H03M13/00 , G11B20/18
CPC分类号： H03M13/116 , G11B20/1833 , H03M13/1111 , H03M13/1171 , H03M13/2957 , H03M13/6325 , H03M13/6343
摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. In one case a data processing system is disclosed that includes a decoder circuit operable to apply a low density parity check algorithm to a decoder input to yield an interim decoded output, where the decoder input is a codeword formed of two bit symbols, and where the decoder input is encoded to yield a last layer including at least two different entry values. In addition, the data processing system includes an inverse mapping circuit operable to remap the interim decoded output to yield an overall decoded output.
摘要翻译：本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法。在一种情况下，公开了一种数据处理系统，其包括解码器电路，其可操作以将低密度奇偶校验算法应用于解码器输入以产生中间解码输出，其中解码器输入是由两个比特符号形成的码字，并且其中解码器输入被编码以产生包括至少两个不同入口值的最后一层。另外，该数据处理系统包括一个反向映射电路，可操作用于重新映射中间解码的输出以产生一个整体解码的输出。

8. 发明授权

US08929009B2 Irregular low density parity check decoder with low syndrome error handling 有权
标题翻译：具有低综合征错误处理的不规则低密度奇偶校验解码器
公开(公告)号：US08929009B2
公开(公告)日：2015-01-06
申请号：US13777381
申请日：2013-02-26
申请人： LSI Corporation
发明人： Shaohua Yang , Anatoli A. Bolotov , Chung-Li Wang , Zongwang Li , Shu Li , Mikhail I Grinchuk
IPC分类号： G11B5/09 , H03M13/00 , G11B20/18 , H03M13/11 , H03M13/27 , H03M13/09
CPC分类号： G11B20/18 , G11B20/1833 , G11B2020/185 , H03M13/09 , H03M13/1111 , H03M13/1128 , H03M13/27 , H03M13/6331
摘要： A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.
摘要翻译：公开了一种数据处理系统，包括数据解码器电路，错误处理电路和综合检查电路。数据解码器电路可操作以将数据解码算法应用于解码器输入以产生解码输出，并计算指示解码输出的误差电平的校正子。错误处理电路可操作以确定解码输出中的任何错误是否涉及用户数据位。综合征检查器电路可操作以至少部分地基于综合征触发误差处理电路。

9. 发明申请

US20140281284A1 MULTI-READ PORT MEMORY 审中-公开
标题翻译：多读端口存储器
公开(公告)号：US20140281284A1
公开(公告)日：2014-09-18
申请号：US13833691
申请日：2013-03-15
申请人： LSI Corporation
发明人： Stefan G. Block , Ting Zhou , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G11C5/04
摘要： A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request.
摘要翻译：一种方法包括接收用于检索存储在三个存储器中的数据的多端口读取请求，每个存储器包括两个存储器模块和奇偶校验模块。多端口读取请求与存储在第一存储器地址处的第一数据，存储在第二存储器地址的第二数据和存储在第三存储器地址的第三数据相关联。当第一存储器地址，第二存储器地址和第三存储器地址与第一存储器模块相关联时，从第一存储器模块检索第一数据，使用来自第二存储器模块和第一奇偶校验模块的数据重建第二数据并且使用来自第四存储器模块和第七存储器模块的数据来重建第三数据。响应于多端口读取请求而提供第一数据，第二数据和第三数据。

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