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1. 发明授权

US06473887B1 Inclusion of global wires in capacitance extraction 失效
标题翻译：将全局线插入电容提取中
公开(公告)号：US06473887B1
公开(公告)日：2002-10-29
申请号：US09560065
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz , Edward W. Seibert
发明人： L. William Dewey, III , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.
摘要翻译：在集成电路设计期间进行电容提取的方法和结构包括输入指定的布线密度和设计要求，根据设计要求确定线段的最小间距，根据布线密度计算透明度因子，计算出在集成电路中存在假想虚线的横向电容，并且基于透明度因子计算垂直电容。

2. 发明授权

US06519752B1 Method of performing parasitic extraction for a multi-fingered transistor 失效
标题翻译：对多指晶体管进行寄生提取的方法
公开(公告)号：US06519752B1
公开(公告)日：2003-02-11
申请号：US09561096
申请日：2000-04-28
申请人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
发明人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.
摘要翻译：一种用于对多指装置执行寄生提取的方法和结构，包括：建立装置的手指的最大处理宽度，将超过最大宽度的装置的手指分成子手指，确定手指中是否有手指子手指具有类似的特征，将具有类似特征的手指和子手指组合成组合手指，并从手指，子手指和组合手指中提取寄生值。

3. 发明授权

US06430729B1 Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing 失效
标题翻译：用于通过动态偏置来保持寄生提取的3西格玛过程公差的过程和系统
公开(公告)号：US06430729B1
公开(公告)日：2002-08-06
申请号：US09494975
申请日：2000-01-31
申请人： L. William Dewey , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert
发明人： L. William Dewey , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.
摘要翻译：一种用于确定集成电路中的寄生元件的特性的方法的方法和结构，包括：识别集成电路中的器件的制造工艺参数，基于制造工艺参数计算每个器件的寄生性能分布，组合寄生每个器件的性能分布成为净寄生值，并且基于净寄生值形成参数化模型。

4. 发明授权

US5761080A Method and apparatus for modeling capacitance in an integrated circuit 失效
标题翻译：用于对集成电路中的电容进行建模的方法和装置
公开(公告)号：US5761080A
公开(公告)日：1998-06-02
申请号：US561647
申请日：1995-11-22
申请人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
发明人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , Y10S706/921
摘要： According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.
摘要翻译：根据本实施例，公开了一种用于计算半导体器件中的寄生电容的方法。根据优选方法，提供了包含半导体器件的形状的布局文件。然后将布局文件的尺寸调整为晶圆尺寸，以反映实际的生产设备。然后，布局文件的形状被分割成更简单的形状，通常是称为块的邻接矩形。然后，每个瓦片被分解成重叠和边缘电容分量，每个部件相对于其电容元件具有均匀的电容环境。因此，可以有效利用资源来准确地计算半导体器件的寄生电容。此外，优选实施例容易适应于广泛的技术类型。

5. 发明授权

US08191030B2 Identifying parasitic diode(s) in an integrated circuit physical design 有权
标题翻译：识别集成电路物理设计中的寄生二极管
公开(公告)号：US08191030B2
公开(公告)日：2012-05-29
申请号：US12337061
申请日：2008-12-17
申请人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
发明人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
摘要翻译：一种方法包括通过电路布局将结的第一和第二端跟踪到相关联的电源，以确定它们各自定义的偏置值。该方法还包括比较每个端子的限定的偏置值，以便基于比较来确定该结是正向偏置的。

6. 发明授权

US07490303B2 Identifying parasitic diode(s) in an integrated circuit physical design 失效
标题翻译：识别集成电路物理设计中的寄生二极管
公开(公告)号：US07490303B2
公开(公告)日：2009-02-10
申请号：US11276511
申请日：2006-03-03
申请人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
发明人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
摘要翻译：一种方法包括通过电路布局将结的第一和第二端跟踪到相关联的电源，以确定它们各自定义的偏置值。该方法还包括比较每个端子的限定的偏置值，以便基于比较来确定该结是正向偏置的。

7. 发明申请

US20130067425A1 IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN 失效
公开(公告)号：US20130067425A1
公开(公告)日：2013-03-14
申请号：US13471623
申请日：2012-05-15
申请人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
发明人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.

8. 发明授权

US08756554B2 Identifying parasitic diode(s) in an integrated circuit physical design 失效
标题翻译：识别集成电路物理设计中的寄生二极管
公开(公告)号：US08756554B2
公开(公告)日：2014-06-17
申请号：US13471623
申请日：2012-05-15
申请人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
发明人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
摘要翻译：一种方法包括通过电路布局将结的第一和第二端跟踪到相关联的电源，以确定它们各自定义的偏置值。该方法还包括比较每个端子的限定的偏置值，以便基于比较来确定该结是正向偏置的。

9. 发明申请

US20090150842A1 IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN 有权
标题翻译：识别集成电路中的PARASITIC DIODE（S）物理设计
公开(公告)号：US20090150842A1
公开(公告)日：2009-06-11
申请号：US12337061
申请日：2008-12-17
申请人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
发明人： Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
摘要翻译：一种方法包括通过电路布局将结的第一和第二端跟踪到相关联的电源，以确定它们各自定义的偏置值。该方法还包括比较每个端子的限定的偏置值，以便基于比较来确定该结是正向偏置的。

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