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1. 发明申请

US20080220611A1 Method of forming fine patterns of semiconductor devices using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US20080220611A1
公开(公告)日：2008-09-11
申请号：US12073502
申请日：2008-03-06
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
IPC分类号： H01L21/308
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.
摘要翻译：根据示例性实施例的形成半导体器件的精细图案的方法可以包括通过将待蚀刻的蚀刻膜上的第一掩模图案和缓冲掩模图案堆叠在衬底上来形成多个多层掩模图案，在蚀刻在多个多层掩模图案之间的空间中的膜，第二掩模图案，去除第二掩模图案以暴露第一掩模图案的上表面，以及通过使用第一和第二掩模图案蚀刻蚀刻膜形成精细图案作为蚀刻掩模该示例性实施例可以导致在单个基板上以不同间距形成不同尺寸。

2. 发明授权

US07935635B2 Method of forming fine patterns of semiconductor devices using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US07935635B2
公开(公告)日：2011-05-03
申请号：US12073502
申请日：2008-03-06
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.
摘要翻译：根据示例性实施例的形成半导体器件的精细图案的方法可以包括通过将待蚀刻的蚀刻膜上的第一掩模图案和缓冲掩模图案堆叠在衬底上来形成多个多层掩模图案，在蚀刻在多个多层掩模图案之间的空间中的膜，第二掩模图案，去除第二掩模图案以暴露第一掩模图案的上表面，以及通过使用第一和第二掩模图案蚀刻蚀刻膜形成精细图案作为蚀刻掩模该示例性实施例可以导致在单个基板上以不同间距形成不同尺寸。

3. 发明申请

US20080090418A1 Method for forming fine patterns of a semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US20080090418A1
公开(公告)日：2008-04-17
申请号：US11730292
申请日：2007-03-30
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee , Je-woo Han
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee , Je-woo Han
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088 , H01L21/32139 , Y10S438/947
摘要： A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.
摘要翻译：公开了一种用于形成半导体器件的精细图案的方法。该方法包括在衬底上形成蚀刻膜，在蚀刻膜上形成保护膜，在保护膜上形成硬掩模层，以及在硬掩模层上形成以第一间距为特征的多个第一掩模图案。该方法还包括形成多个第二掩模图案，通过使用第一和第二掩模图案作为蚀刻掩模蚀刻硬掩模层，形成暴露部分保护膜的硬掩模图案，以及去除第一和第二掩模图案。该方法还包括暴露部分蚀刻膜并且通过使用至少硬掩模图案作为蚀刻掩模蚀刻蚀刻膜来形成多个精细图案，其特征在于具有等于第一间距的一半的第二间距。

4. 发明授权

US07601647B2 Method of forming fine patterns of semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件精细图案的方法
公开(公告)号：US07601647B2
公开(公告)日：2009-10-13
申请号：US11810200
申请日：2007-06-05
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32137
摘要： A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.
摘要翻译：形成半导体器件的精细图案的方法包括通过改变产生聚合物副产物的量来双重蚀刻，以在具有不同图案密度的区域中蚀刻具有不同厚度的膜。在第一蚀刻中，在第一蚀刻环境下，在低密度图案区域和高密度图案区域中的缓冲层和硬掩模层上执行反应离子蚀刻（RIE），直到蚀刻膜暴露于低使用掩模图案作为蚀刻掩模的密度图案区域。在用于形成硬掩模图案的第二蚀刻中，使用掩模图案作为蚀刻掩模，硬掩模层被蚀刻直到蚀刻膜在高密度图案区域中暴露，同时在低密度图案区域中的蚀刻膜上聚集聚合物副产物，在第二蚀刻环境下具有比在第一蚀刻环境中产生的聚合物副产物大的密度图案区域。

5. 发明授权

US07576010B2 Method of forming pattern using fine pitch hard mask 有权
标题翻译：使用细间距硬掩模形成图案的方法
公开(公告)号：US07576010B2
公开(公告)日：2009-08-18
申请号：US11699476
申请日：2007-01-30
申请人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
发明人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.
摘要翻译：一种形成第一硬掩模图案的方法，所述第一硬掩模图案包括在第一方向上形成在蚀刻目标层上并具有第一间距的多个第一线图案。第三层形成在第一硬掩模图案的侧壁和上表面上，使得第三层包括具有形成在两个相邻的第一线图案之间的凹部的顶表面。形成包括在凹部内沿第一方向延伸的多个第二线图案的第二硬掩模图案。然后，第三层被各向异性蚀刻以选择性地暴露第一线图案和第二线图案之间的蚀刻目标层。然后，使用第一硬掩模图案和第二硬掩模图案作为蚀刻掩模对蚀刻目标层进行各向异性蚀刻。

6. 发明申请

US20080131793A1 Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same 有权
标题翻译：用于形成具有细间距的硬掩模图案的方法和使用其形成半导体器件的方法
公开(公告)号：US20080131793A1
公开(公告)日：2008-06-05
申请号：US11978719
申请日：2007-10-30
申请人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
发明人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
IPC分类号： G03F7/40 , G03F1/00
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088
摘要： A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.
摘要翻译：一种形成硬掩模图案的方法包括：在基板上顺序地形成由具有不同蚀刻选择性的材料形成的第一，第二和第三硬掩模层，在第三硬掩模层上形成具有第一间距的第一牺牲图案，形成第四硬在第一牺牲图案之间具有第二间距的掩模图案，第二间距基本上等于第一间距的大约1/2，使用第四硬掩模图案作为蚀刻掩模，图案化第三硬掩模层以形成第三硬掩模图案，图案化第二硬掩模层，以使用第三和第四硬掩模图案作为蚀刻掩模形成第二硬掩模图案，以及使用第二和第三硬掩模图案使第一硬掩模层形成第一硬掩模图案，其间具有第二间距，作为蚀刻掩模。

7. 发明申请

US20070123037A1 Method of forming pattern using fine pitch hard mask 有权
标题翻译：使用细间距硬掩模形成图案的方法
公开(公告)号：US20070123037A1
公开(公告)日：2007-05-31
申请号：US11699476
申请日：2007-01-30
申请人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
发明人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.
摘要翻译：一种形成第一硬掩模图案的方法，所述第一硬掩模图案包括在第一方向上形成在蚀刻目标层上并具有第一间距的多个第一线图案。第三层形成在第一硬掩模图案的侧壁和上表面上，使得第三层包括具有形成在两个相邻的第一线图案之间的凹部的顶表面。形成包括在凹部内沿第一方向延伸的多个第二线图案的第二硬掩模图案。然后，第三层被各向异性蚀刻以选择性地暴露第一线图案和第二线图案之间的蚀刻目标层。然后，使用第一硬掩模图案和第二硬掩模图案作为蚀刻掩模对蚀刻目标层进行各向异性蚀刻。

8. 发明授权

US07998874B2 Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same 有权
标题翻译：用于形成具有细间距的硬掩模图案的方法和使用其形成半导体器件的方法
公开(公告)号：US07998874B2
公开(公告)日：2011-08-16
申请号：US11978719
申请日：2007-10-30
申请人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
发明人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/461 , C03C15/00
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088
摘要： A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.
摘要翻译：一种形成硬掩模图案的方法包括：在基板上顺序地形成由具有不同蚀刻选择性的材料形成的第一，第二和第三硬掩模层，在第三硬掩模层上形成具有第一间距的第一牺牲图案，形成第四硬在第一牺牲图案之间具有第二间距的掩模图案，第二间距基本上等于第一间距的大约1/2，使用第四硬掩模图案作为蚀刻掩模，图案化第三硬掩模层以形成第三硬掩模图案，图案化第二硬掩模层，以使用第三和第四硬掩模图案作为蚀刻掩模形成第二硬掩模图案，以及使用第二和第三硬掩模图案使第一硬掩模层形成第一硬掩模图案，其间具有第二间距，作为蚀刻掩模。

9. 发明授权

US07550391B2 Method for forming fine patterns of a semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US07550391B2
公开(公告)日：2009-06-23
申请号：US11730292
申请日：2007-03-30
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee , Je-woo Han
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee , Je-woo Han
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088 , H01L21/32139 , Y10S438/947
摘要： A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.
摘要翻译：公开了一种用于形成半导体器件的精细图案的方法。该方法包括在衬底上形成蚀刻膜，在蚀刻膜上形成保护膜，在保护膜上形成硬掩模层，以及在硬掩模层上形成以第一间距为特征的多个第一掩模图案。该方法还包括形成多个第二掩模图案，通过使用第一和第二掩模图案作为蚀刻掩模蚀刻硬掩模层，形成暴露部分保护膜的硬掩模图案，以及去除第一和第二掩模图案。该方法还包括暴露部分蚀刻膜并且通过使用至少硬掩模图案作为蚀刻掩模蚀刻蚀刻膜来形成多个精细图案，其特征在于具有等于第一间距的一半的第二间距。

10. 发明申请

US20080188083A1 Method of forming fine patterns of semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件精细图案的方法
公开(公告)号：US20080188083A1
公开(公告)日：2008-08-07
申请号：US11810200
申请日：2007-06-05
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32137
摘要： A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.
摘要翻译：形成半导体器件的精细图案的方法包括通过改变产生聚合物副产物的量来双重蚀刻，以在具有不同图案密度的区域中蚀刻具有不同厚度的膜。在第一蚀刻中，在第一蚀刻环境下，在低密度图案区域和高密度图案区域中的缓冲层和硬掩模层上执行反应离子蚀刻（RIE），直到蚀刻膜暴露于低使用掩模图案作为蚀刻掩模的密度图案区域。在用于形成硬掩模图案的第二蚀刻中，使用掩模图案作为蚀刻掩模，硬掩模层被蚀刻直到蚀刻膜在高密度图案区域中暴露，同时在低密度图案区域中的聚合物副产物上积累在蚀刻膜上，在第二蚀刻环境下具有比在第一蚀刻环境中产生的聚合物副产物大的密度图案区域。

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