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1. 发明授权

US07670957B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07670957B2
公开(公告)日：2010-03-02
申请号：US11356509
申请日：2006-02-17
申请人： Ki-Won Nam , Kyung-Won Lee
发明人： Ki-Won Nam , Kyung-Won Lee
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32137 , H01L21/32139 , H01L27/105 , H01L27/1052
摘要： A method for fabricating a semiconductor device is provided. The method includes sequentially forming etch target layers, a hard mask layer and an anti-reflective coating layer, selectively etching the anti-reflective coating layer and the hard mask layer using a gas generating polymers, thereby increasing a line width of a bottom portion of the hard mask layer due to the polymers, and etching the etch target layers using a patterned hard mask layer with the increased line width.
摘要翻译：提供一种制造半导体器件的方法。该方法包括顺序地形成蚀刻目标层，硬掩模层和抗反射涂层，使用产生气体的聚合物选择性地蚀刻抗反射涂层和硬掩模层，从而增加底层部分的线宽由于聚合物引起的硬掩模层，并且使用具有增加的线宽度的图案化硬掩模层来蚀刻蚀刻目标层。

2. 发明授权

US07592268B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07592268B2
公开(公告)日：2009-09-22
申请号：US11295902
申请日：2005-12-06
申请人： Ki-Won Nam , Kyung-Won Lee
发明人： Ki-Won Nam , Kyung-Won Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/76897 , H01L21/76832 , H01L21/76834 , H01L27/10873
摘要： A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer oxide layer and a nitride layer on the oxide layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：通过进行蚀刻工艺在衬底上形成多条栅极线; 通过使用原子层沉积（ALD）方法在栅极线和衬底上形成氧化物层; 并在氧化物层上依次形成缓冲氧化物层和氮化物层。

3. 发明申请

US20070184664A1 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region 失效
公开(公告)号：US20070184664A1
公开(公告)日：2007-08-09
申请号：US11654460
申请日：2007-01-17
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/461
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.

4. 发明申请

US20060276018A1 Method for fabricating semiconductor device 失效
公开(公告)号：US20060276018A1
公开(公告)日：2006-12-07
申请号：US11295902
申请日：2005-12-06
申请人： Ki-Won Nam , Kyung-Won Lee
发明人： Ki-Won Nam , Kyung-Won Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76897 , H01L21/76832 , H01L21/76834 , H01L27/10873
摘要： A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer oxide layer and a nitride layer on the oxide layer.

5. 发明授权

US07803710B2 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region 失效
标题翻译：制造能够减小外围区域临界尺寸的半导体器件的方法
公开(公告)号：US07803710B2
公开(公告)日：2010-09-28
申请号：US12484748
申请日：2009-06-15
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/306
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
摘要翻译：一种半导体器件的制造方法，其中周边区域的临界尺寸减小。该方法包括以下步骤：在包括单元区域和周边区域的基板上形成氮化硅层; 在氮化硅层上形成氧氮化硅层; 在氮氧化硅层上形成线型光致抗蚀剂图案，使得单元区域中的光致抗蚀剂图案的宽度大于最终图案结构的宽度，并且周边区域中的光致抗蚀剂图案具有减小图案崩溃的发生率的宽度 ; 通过抑制聚合物的产生，蚀刻硅氧氮化物层和氮化硅层，直到剩余的氮氧化硅层和剩余的氮化硅层的宽度小于用作蚀刻掩模的光致抗蚀剂图案的宽度; 并过剩蚀刻剩余的氮化硅层。

6. 发明申请

US20090253263A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE CAPABLE OF DECREASING CRITICAL DIMENSION IN PERIPHERAL REGION 失效
标题翻译：用于制造能够减少外围区域关键尺寸的半导体器件的方法
公开(公告)号：US20090253263A1
公开(公告)日：2009-10-08
申请号：US12484748
申请日：2009-06-15
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/306
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
摘要翻译：一种半导体器件的制造方法，其中周边区域的临界尺寸减小。该方法包括以下步骤：在包括单元区域和周边区域的基板上形成氮化硅层; 在氮化硅层上形成氧氮化硅层; 在氮氧化硅层上形成线型光致抗蚀剂图案，使得单元区域中的光致抗蚀剂图案的宽度大于最终图案结构的宽度，并且周边区域中的光致抗蚀剂图案具有减小图案崩溃的发生率的宽度 ; 通过抑制聚合物的产生，蚀刻硅氧氮化物层和氮化硅层，直到剩余的氮氧化硅层和剩余的氮化硅层的宽度小于用作蚀刻掩模的光致抗蚀剂图案的宽度; 并过剩蚀刻剩余的氮化硅层。

7. 发明授权

US07563721B2 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region 失效
标题翻译：制造能够减小外围区域临界尺寸的半导体器件的方法
公开(公告)号：US07563721B2
公开(公告)日：2009-07-21
申请号：US11654460
申请日：2007-01-17
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/461
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
摘要翻译：一种半导体器件的制造方法，其中周边区域的临界尺寸减小。该方法包括以下步骤：在包括单元区域和周边区域的基板上形成氮化硅层; 在氮化硅层上形成氧氮化硅层; 在氮氧化硅层上形成线型光致抗蚀剂图案，使得单元区域中的光致抗蚀剂图案的宽度大于最终图案结构的宽度，并且周边区域中的光致抗蚀剂图案具有减小图案崩溃的发生率的宽度 ; 通过抑制聚合物的产生，蚀刻硅氧氮化物层和氮化硅层，直到剩余的氮氧化硅层和剩余的氮化硅层的宽度小于用作蚀刻掩模的光致抗蚀剂图案的宽度; 并过剩蚀刻剩余的氮化硅层。

8. 发明申请

US20060292886A1 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060292886A1
公开(公告)日：2006-12-28
申请号：US11356509
申请日：2006-02-17
申请人： Ki-Won Nam , Kyung-Won Lee
发明人： Ki-Won Nam , Kyung-Won Lee
IPC分类号： G03F1/00 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/32139 , H01L27/105 , H01L27/1052
摘要： A method for fabricating a semiconductor device is provided. The method includes sequentially forming etch target layers, a hard mask layer and an anti-reflective coating layer, selectively etching the anti-reflective coating layer and the hard mask layer using a gas generating polymers, thereby increasing a line width of a bottom portion of the hard mask layer due to the polymers, and etching the etch target layers using a patterned hard mask layer with the increased line width.
摘要翻译：提供一种制造半导体器件的方法。该方法包括顺序地形成蚀刻目标层，硬掩模层和抗反射涂层，使用产生气体的聚合物选择性地蚀刻抗反射涂层和硬掩模层，从而增加底层部分的线宽由于聚合物引起的硬掩模层，并且使用具有增加的线宽度的图案化硬掩模层来蚀刻蚀刻目标层。

9. 发明授权

US07179749B2 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region 失效
标题翻译：制造能够减小外围区域临界尺寸的半导体器件的方法
公开(公告)号：US07179749B2
公开(公告)日：2007-02-20
申请号：US11165740
申请日：2005-06-24
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
摘要翻译：一种半导体器件的制造方法，其中周边区域的临界尺寸减小。该方法包括以下步骤：在包括单元区域和周边区域的基板上形成氮化硅层; 在氮化硅层上形成氧氮化硅层; 在氮氧化硅层上形成线型光致抗蚀剂图案，使得单元区域中的光致抗蚀剂图案的宽度大于最终图案结构的宽度，并且周边区域中的光致抗蚀剂图案具有减小图案崩溃的发生率的宽度 ; 通过抑制聚合物的产生，蚀刻硅氧氮化物层和氮化硅层，直到剩余的氮氧化硅层和剩余的氮化硅层的宽度小于用作蚀刻掩模的光致抗蚀剂图案的宽度; 并过剩蚀刻剩余的氮化硅层。

10. 发明申请

US20050287809A1 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region 失效
标题翻译：制造能够减小外围区域临界尺寸的半导体器件的方法
公开(公告)号：US20050287809A1
公开(公告)日：2005-12-29
申请号：US11165740
申请日：2005-06-24
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/8242 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/32 , H01L21/3213
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
摘要翻译：一种半导体器件的制造方法，其中周边区域的临界尺寸减小。该方法包括以下步骤：在包括单元区域和周边区域的基板上形成氮化硅层; 在氮化硅层上形成氮氧化硅层; 在氮氧化硅层上形成线型光致抗蚀剂图案，使得单元区域中的光致抗蚀剂图案的宽度大于最终图案结构的宽度，并且周边区域中的光致抗蚀剂图案具有减小图案崩溃的发生率的宽度 ; 通过抑制聚合物的产生，蚀刻硅氧氮化物层和氮化硅层，直到剩余的氮氧化硅层和剩余的氮化硅层的宽度小于用作蚀刻掩模的光致抗蚀剂图案的宽度; 并过剩蚀刻剩余的氮化硅层。

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