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1. 发明授权

US09007819B2 Magnetic random access memory device and method of writing data therein 有权
标题翻译：磁性随机存取存储器件及其中的数据写入方法
公开(公告)号：US09007819B2
公开(公告)日：2015-04-14
申请号：US13532811
申请日：2012-06-26
申请人： Su-Jin Ahn , Kyung-Tae Nam
发明人： Su-Jin Ahn , Kyung-Tae Nam
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/161
摘要： In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.
摘要翻译：在MRAM装置中写入数据的方法中，在MRAM装置的多个存储单元中选择第一操作单元。第一至第n开关脉冲被顺序地施加到第一操作单元以分别在第一操作单元的第一至第n组存储单元中写入数据。第n开关脉冲的电流电平可以低于第（n-1）个开关脉冲的电流电平，其中n是大于至少1的整数。第n个开关脉冲的脉冲宽度可以窄于的第（n-1）个开关脉冲，其中n是大于至少1的整数。可以对第二操作单元重复该技术。公开了一种装置和系统，其中不同的电流切换脉冲被施加到第一和/或第二操作单元内的多组存储器单元。

2. 发明申请

US20100213558A1 Magnetic Memory Device 有权
标题翻译：磁存储器件
公开(公告)号：US20100213558A1
公开(公告)日：2010-08-26
申请号：US12773451
申请日：2010-05-04
申请人： Jun-Soo Bae , Jang-Eun Lee , Hyun-Jo Kim , Se-Chung Oh , Kyung-Tae Nam
发明人： Jun-Soo Bae , Jang-Eun Lee , Hyun-Jo Kim , Se-Chung Oh , Kyung-Tae Nam
IPC分类号： H01L29/82
CPC分类号： G11C11/15 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F10/3272 , H01F10/3281 , H01F41/302 , H01L43/08
摘要： A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.
摘要翻译：提供磁存储器件。磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。在存储和无引导模式之间插入一个自由的反转模式。自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。

3. 发明授权

US07372090B2 Magnetic random access memory device and method of forming the same 有权
标题翻译：磁性随机存取存储器件及其形成方法
公开(公告)号：US07372090B2
公开(公告)日：2008-05-13
申请号：US11347280
申请日：2006-02-06
申请人： Se-Chung Oh , Jang-Eun Lee , Jun-Soo Bae , Hyun-Jo Kim , Kyung-Tae Nam , Young-Ki Ha
发明人： Se-Chung Oh , Jang-Eun Lee , Jun-Soo Bae , Hyun-Jo Kim , Kyung-Tae Nam , Young-Ki Ha
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： G11C11/16 , B82Y10/00 , B82Y25/00 , G11B5/3909 , H01L27/228 , H01L43/08 , H01L43/12 , Y10T29/49034 , Y10T29/49044
摘要： Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.
摘要翻译：本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交。形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作，并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

4. 发明申请

US20070230242A1 Methods of Forming Magnetic Random Access Memory Devices Including Contact Plugs Between Magnetic Tunnel Junction Structures and Substrates 审中-公开
标题翻译：在磁性隧道结结构和基板之间形成包括接触塞的磁性随机存取存储器件的方法
公开(公告)号：US20070230242A1
公开(公告)日：2007-10-04
申请号：US11762319
申请日：2007-06-13
申请人： Jang Lee , Se-Chung Oh , Jun-Soo Bae , Hyun-Jo Kim , Young-Ki Ha , Kyung-Tae Nam
发明人： Jang Lee , Se-Chung Oh , Jun-Soo Bae , Hyun-Jo Kim , Young-Ki Ha , Kyung-Tae Nam
IPC分类号： G11C11/02
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161
摘要： A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.
摘要翻译：磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。还讨论了相关方法。

5. 发明申请

US20070206411A1 Magnetic Random Access Memory Devices Including Contact Plugs Between Magnetic Tunnel Junction Structures and Substrates and Related Methods 审中-公开
标题翻译：包括磁性隧道结结构和基板之间的接触插塞的磁性随机存取存储器件及相关方法
公开(公告)号：US20070206411A1
公开(公告)日：2007-09-06
申请号：US11746810
申请日：2007-05-10
申请人： Jang Lee , Se-Chung Oh , Jun-Soo Bae , Hyun-Jo Kim , Young-Ki Ha , Kyung-Tae Nam
发明人： Jang Lee , Se-Chung Oh , Jun-Soo Bae , Hyun-Jo Kim , Young-Ki Ha , Kyung-Tae Nam
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161
摘要： A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.
摘要翻译：磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。还讨论了相关方法。

6. 发明申请

US20060027846A1 Magnetic random access memory devices including contact plugs between magnetic tunnel junction structures and substrates and related methods 审中-公开
标题翻译：磁性随机存取存储器件包括磁性隧道结结构和衬底之间的接触插塞以及相关方法
公开(公告)号：US20060027846A1
公开(公告)日：2006-02-09
申请号：US11145478
申请日：2005-06-03
申请人： Jang-Eun Lee , Se-Chung Oh , Jun-Soo Bae , Hyun-Jo Kim , Young-Ki Ha , Kyung-Tae Nam
发明人： Jang-Eun Lee , Se-Chung Oh , Jun-Soo Bae , Hyun-Jo Kim , Young-Ki Ha , Kyung-Tae Nam
IPC分类号： H01L29/94
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161
摘要： A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.
摘要翻译：磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。还讨论了相关方法。

7. 发明授权

US08345467B2 Resistive memory devices including selected reference memory cells operating responsive to read operations 有权
标题翻译：电阻式存储器件包括响应于读取操作而工作的选择的参考存储器单元
公开(公告)号：US08345467B2
公开(公告)日：2013-01-01
申请号：US13219582
申请日：2011-08-26
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0054 , G11C2213/32 , G11C2213/79
摘要： A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
摘要翻译：基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。

8. 发明申请

US20100233849A1 Methods of Forming Resistive Memory Devices 有权
标题翻译：形成电阻式存储器件的方法
公开(公告)号：US20100233849A1
公开(公告)日：2010-09-16
申请号：US12784230
申请日：2010-05-20
申请人： Jang Eun Lee , Dae-Kyom Kim , Jun-Ho Jeong , Se-Chung Oh , Kyung-Tae Nam , Hyun-Jun Sim
发明人： Jang Eun Lee , Dae-Kyom Kim , Jun-Ho Jeong , Se-Chung Oh , Kyung-Tae Nam , Hyun-Jun Sim
IPC分类号： H01L21/36
CPC分类号： H01L45/04 , H01L27/2418 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1633
摘要： Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.
摘要翻译：形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。还公开了相关的电阻式存储器件。

9. 发明授权

US07750336B2 Resistive memory devices and methods of forming resistive memory devices 有权
标题翻译：电阻式存储器件和形成电阻式存储器件的方法
公开(公告)号：US07750336B2
公开(公告)日：2010-07-06
申请号：US12207889
申请日：2008-09-10
申请人： Jang-Eun Lee , Dae-Kyom Kim , Jun-Ho Jeong , Se-Chung Oh , Kyung-Tae Nam , Hyun-Jun Sim
发明人： Jang-Eun Lee , Dae-Kyom Kim , Jun-Ho Jeong , Se-Chung Oh , Kyung-Tae Nam , Hyun-Jun Sim
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L27/2418 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1633
摘要： Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.
摘要翻译：形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。还公开了相关的电阻式存储器件。

10. 发明授权

US07672155B2 Resistive memory devices including selected reference memory cells 失效
标题翻译：电阻式存储器件包括所选择的参考存储单元
公开(公告)号：US07672155B2
公开(公告)日：2010-03-02
申请号：US12265941
申请日：2008-11-06
申请人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
发明人： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1673
摘要： A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.
摘要翻译：磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为向读取期间未选择访问的第一或第二存储器单元施加第二偏置电压操作。

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