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1. 发明申请

US20100068841A1 Thin Film Transistor Array Panel and Method of Manufacturing the Same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20100068841A1
公开(公告)日：2010-03-18
申请号：US12433743
申请日：2009-04-30
申请人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
发明人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/4908 , H01L29/66757
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上形成多晶硅半导体层; 在所述半导体层上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 通过掺杂半导体层中的导电杂质形成源区和漏区; 形成覆盖所述栅电极的层间绝缘层; 形成分别连接到源区和漏区的源电极和漏电极; 形成覆盖源极和漏极的钝化层; 形成连接到所述漏电极的像素电极; 以及在形成从半导体层，栅电极，源极和漏极以及像素电极中选择的一个时形成第一对准键，其中从半导体层，栅电极，源电极和漏电极中选择一个，并且至少通过使用光致抗蚀剂图案作为蚀刻掩模的光刻工艺形成像素电极，并且在与光致抗蚀剂图案相同的层处形成完全覆盖第一对准键的第二对准键。

2. 发明授权

US07803672B2 Thin film transistor array panel and method of manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07803672B2
公开(公告)日：2010-09-28
申请号：US12433743
申请日：2009-04-30
申请人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
发明人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/4908 , H01L29/66757
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上形成多晶硅半导体层; 在所述半导体层上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 通过掺杂半导体层中的导电杂质形成源区和漏区; 形成覆盖所述栅电极的层间绝缘层; 形成分别连接到源区和漏区的源电极和漏电极; 形成覆盖源极和漏极的钝化层; 形成连接到所述漏电极的像素电极; 以及在形成从半导体层，栅电极，源极和漏极以及像素电极中选择的一个时形成第一对准键，其中从半导体层，栅电极，源电极和漏电极中选择一个，并且至少通过使用光致抗蚀剂图案作为蚀刻掩模的光刻工艺形成像素电极，并且在与光致抗蚀剂图案相同的层处形成完全覆盖第一对准键的第二对准键。

3. 发明授权

US07528021B2 Thin film transistor array panel and method of manufacturing the same 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07528021B2
公开(公告)日：2009-05-05
申请号：US11229245
申请日：2005-09-15
申请人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
发明人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/4908 , H01L29/66757
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上形成多晶硅半导体层; 在所述半导体层上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 通过掺杂半导体层中的导电杂质形成源区和漏区; 形成覆盖所述栅电极的层间绝缘层; 形成分别连接到源区和漏区的源电极和漏电极; 形成覆盖源极和漏极的钝化层; 形成连接到所述漏电极的像素电极; 以及在形成从半导体层，栅电极，源极和漏极以及像素电极中选择的一个时形成第一对准键，其中从半导体层，栅电极，源电极和漏电极中选择一个，并且至少通过使用光致抗蚀剂图案作为蚀刻掩模的光刻工艺形成像素电极，并且在与光致抗蚀剂图案相同的层处形成完全覆盖第一对准键的第二对准键。

4. 发明申请

US20060060858A1 Thin film transistor array panel and method of manufacturing the same 失效
公开(公告)号：US20060060858A1
公开(公告)日：2006-03-23
申请号：US11229245
申请日：2005-09-15
申请人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
发明人： Kyung-Min Park , Jin-Goo Jung , Chun-Gi You , Jae-Byoung Chae , Tae-Ill Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/4908 , H01L29/66757
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.

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