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1. 发明授权

US07898850B2 Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells 有权
标题翻译：存储单元，电子系统，形成存储单元的方法，以及编程存储单元的方法
公开(公告)号：US07898850B2
公开(公告)日：2011-03-01
申请号：US11871339
申请日：2007-10-12
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

2. 发明授权

US08228743B2 Memory cells containing charge-trapping zones 有权
标题翻译：含有电荷捕获区的存储单元
公开(公告)号：US08228743B2
公开(公告)日：2012-07-24
申请号：US13024903
申请日：2011-02-10
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A Weimer , Arup Bhattacharyya
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

3. 发明申请

US20110133268A1 Memory Cells 有权
标题翻译：记忆细胞
公开(公告)号：US20110133268A1
公开(公告)日：2011-06-09
申请号：US13024903
申请日：2011-02-10
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D.V. Nirmal Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D.V. Nirmal Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
IPC分类号： H01L29/792
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

4. 发明申请

US20090097320A1 Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells 有权
标题翻译：记忆单元，电子系统，形成记忆单元的方法，以及编程记忆单元的方法
公开(公告)号：US20090097320A1
公开(公告)日：2009-04-16
申请号：US11871339
申请日：2007-10-12
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

5. 发明申请

US20090001443A1 NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC 审中-公开
标题翻译：具有多层阻塞介质的非易失性存储单元
公开(公告)号：US20090001443A1
公开(公告)日：2009-01-01
申请号：US11771482
申请日：2007-06-29
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Rhett T. Brewer , Thomas M. Graettinger , Nirmal Ramaswamy , M. Noel Rocklein
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Rhett T. Brewer , Thomas M. Graettinger , Nirmal Ramaswamy , M. Noel Rocklein
IPC分类号： H01L29/788
CPC分类号： H01L29/513 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234
摘要： Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.
摘要翻译：公开了一种非易失性存储单元。非易失性存储单元包括具有有源区的基板。底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。电荷存储节点设置在底部电介质层的上方。此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。在多个顶部电介质层中，设置有控制栅极。

6. 发明申请

US20110147827A1 Flash memory with partially removed blocking dielectric in the wordline direction 审中-公开
标题翻译：在字线方向上部分去除阻塞电介质的闪存
公开(公告)号：US20110147827A1
公开(公告)日：2011-06-23
申请号：US12655090
申请日：2009-12-23
申请人： Fatma Arzum Simsek-Ege , Sanh Tang , Nirmal Ramaswamy , Thomas M. Graettinger , Kyu S. Min , Tejas Krishnamohan , Srivardhan Gowda
发明人： Fatma Arzum Simsek-Ege , Sanh Tang , Nirmal Ramaswamy , Thomas M. Graettinger , Kyu S. Min , Tejas Krishnamohan , Srivardhan Gowda
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/40117 , H01L29/792
摘要： The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.
摘要翻译：本公开一般涉及非易失性存储器的制造。在至少一个实施例中，本公开涉及形成分层阻挡电介质，其具有沿字线方向的一部分。

7. 发明授权

US07989289B2 Floating gate structures 有权
标题翻译：浮门结构
公开(公告)号：US07989289B2
公开(公告)日：2011-08-02
申请号：US12165272
申请日：2008-06-30
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L21/28052 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.
摘要翻译：通常描述浮栅结构。在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率。与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

8. 发明申请

US20090321809A1 GRADED OXY-NITRIDE TUNNEL BARRIER 审中-公开
标题翻译：分级氧化铁隧道障碍物
公开(公告)号：US20090321809A1
公开(公告)日：2009-12-31
申请号：US12165219
申请日：2008-06-30
申请人： Nirmal Ramaswamy , Tejas Krishnamohan , Kyu Min , Thomas M. Graettinger
发明人： Nirmal Ramaswamy , Tejas Krishnamohan , Kyu Min , Thomas M. Graettinger
IPC分类号： H01L29/788 , H01L21/469
CPC分类号： H01L21/02332 , H01L21/0214 , H01L21/02145 , H01L21/02148 , H01L21/02159 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02337 , H01L21/0234 , H01L21/3143 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/513
摘要： Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed.
摘要翻译：简而言之，公开了一种用于包括梯度氧化氮层的非易失性存储器件的隧道势垒。

9. 发明申请

US20090283817A1 FLOATING GATE STRUCTURES 有权
标题翻译：浮动门结构
公开(公告)号：US20090283817A1
公开(公告)日：2009-11-19
申请号：US12165272
申请日：2008-06-30
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28052 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.
摘要翻译：通常描述浮栅结构。在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率。与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

10. 发明申请

US20130264628A1 USE OF ETCH PROCESS POST WORDLINE DEFINITION TO IMPROVE DATA RETENTION IN A FLASH MEMORY DEVICE 有权
标题翻译： ETCH过程的使用在字幕定义中改进闪存存储器件中的数据保持
公开(公告)号：US20130264628A1
公开(公告)日：2013-10-10
申请号：US13993444
申请日：2011-09-22
申请人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
发明人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
IPC分类号： H01L21/306 , H01L29/788
CPC分类号： H01L21/30604 , H01L21/76 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用蚀刻处理后字幕定义相关的技术和配置以改善闪存设备中的数据保持。在一个实施例中，一种方法包括在衬底上形成多个字线结构，其中多个字线结构中的各个字线结构包括具有导电材料的控制栅极和在控制栅极上形成有电绝缘材料的盖，沉积电绝缘材料以在单个字线结构的表面上形成衬垫，以及蚀刻衬垫以去除衬垫的至少一部分。可以描述和/或要求保护其他实施例。

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