专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07728375B2 Semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US07728375B2
公开(公告)日：2010-06-01
申请号：US12219358
申请日：2008-07-21
申请人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
发明人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10855 , H01L27/10888
摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.
摘要翻译：示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。半导体存储器件可以包括半导体衬底上的第一层间绝缘层。位线可以在第一层间绝缘层上沿第一方向布置。位线接触焊盘可以设置在第一层间绝缘层中并电连接到位线。存储接触焊盘可以设置在第一层间绝缘层中。位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。

2. 发明申请

US20090026515A1 Semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20090026515A1
公开(公告)日：2009-01-29
申请号：US12219358
申请日：2008-07-21
申请人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
发明人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
IPC分类号： H01L29/94 , H01L21/4763
CPC分类号： H01L28/91 , H01L27/10855 , H01L27/10888
摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.
摘要翻译：示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。半导体存储器件可以包括半导体衬底上的第一层间绝缘层。位线可以在第一层间绝缘层上沿第一方向布置。位线接触焊盘可以设置在第一层间绝缘层中并且电连接到位线。存储接触焊盘可以设置在第一层间绝缘层中。位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。

3. 发明申请

US20060040443A1 Methods of forming capacitor electrodes using fluorine and oxygen 失效
标题翻译：使用氟和氧形成电容器电极的方法
公开(公告)号：US20060040443A1
公开(公告)日：2006-02-23
申请号：US11154152
申请日：2005-06-16
申请人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
发明人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
IPC分类号： H01L21/8244
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/10852 , H01L27/11502 , H01L27/11507
摘要： A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.
摘要翻译：形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

4. 发明授权

US07329574B2 Methods of forming capacitor electrodes using fluorine and oxygen 失效
标题翻译：使用氟和氧形成电容器电极的方法
公开(公告)号：US07329574B2
公开(公告)日：2008-02-12
申请号：US11154152
申请日：2005-06-16
申请人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
发明人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/10852 , H01L27/11502 , H01L27/11507
摘要： A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.
摘要翻译：形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

5. 发明申请

US20090186471A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE FOR REDUCING THERMAL BURDEN ON IMPURITY REGIONS OF PERIPHERAL CIRCUIT REGION 失效
标题翻译：制造半导体器件的方法，用于减少外围电路区的绝缘区域的热冲击
公开(公告)号：US20090186471A1
公开(公告)日：2009-07-23
申请号：US12321335
申请日：2009-01-20
申请人： Kyoung-Ho Jung , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Joon-Seok Moon , Cheol-Kyu Lee , Sung-Il Cho
发明人： Kyoung-Ho Jung , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Joon-Seok Moon , Cheol-Kyu Lee , Sung-Il Cho
IPC分类号： H01L21/426 , H01L21/04
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/82385
摘要： A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
摘要翻译：制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。可以在电池活性区域中形成第一电池杂质区域。可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。牺牲绝缘层可以与外围栅极图案相邻地去除。第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

6. 发明授权

US07879703B2 Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region 失效
标题翻译：制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法
公开(公告)号：US07879703B2
公开(公告)日：2011-02-01
申请号：US12321335
申请日：2009-01-20
申请人： Kyoung-Ho Jung , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Joon-Seok Moon , Cheol-Kyu Lee , Sung-Il Cho
发明人： Kyoung-Ho Jung , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Joon-Seok Moon , Cheol-Kyu Lee , Sung-Il Cho
IPC分类号： H01L21/425
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/82385
摘要： A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
摘要翻译：制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。可以在电池活性区域中形成第一电池杂质区域。可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。牺牲绝缘层可以与外围栅极图案相邻地去除。第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

7. 发明申请

US20090042396A1 METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELECTIVE ETCHING OF AN ACTIVE REGION THROUGH A HARDMASK 有权
标题翻译：通过HARDMASK选择性蚀刻活性区域形成半导体器件的方法
公开(公告)号：US20090042396A1
公开(公告)日：2009-02-12
申请号：US12187895
申请日：2008-08-07
申请人： Heung-Sik Park , Jun-Ho Yoon , Cheol-Kyu Lee , Joon-Soo Park
发明人： Heung-Sik Park , Jun-Ho Yoon , Cheol-Kyu Lee , Joon-Soo Park
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/3065 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.
摘要翻译：提供一种制造半导体器件的方法。该方法可以包括在其上限定有源区和隔离区的衬底上形成包括下硬掩模膜和上硬掩模膜的硬掩模膜，并对硬掩模膜进行构图以提供部分暴露有源区的硬掩模图案和隔离地区。可以使用硬掩模图案作为蚀刻掩模将蚀刻剂施加到有源和隔离区域，以在衬底的有源区域中形成沟槽，同时避免基本上蚀刻暴露于蚀刻剂的隔离区域，并且可以在栅极上形成栅极沟。

8. 发明授权

US07226867B2 Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas 失效
标题翻译：使用掩模蚀刻金属层的方法，半导体器件的金属化方法，蚀刻金属层的方法和蚀刻气体
公开(公告)号：US07226867B2
公开(公告)日：2007-06-05
申请号：US10419075
申请日：2003-04-21
申请人： Seung-Young Son , Cheol-Kyu Lee , Chang-Jin Kang , Byeong-Yun Nam
发明人： Seung-Young Son , Cheol-Kyu Lee , Chang-Jin Kang , Byeong-Yun Nam
IPC分类号： H01L21/302
CPC分类号： C23F4/00 , H01L21/32136 , H01L21/32139
摘要： Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.
摘要翻译：提供了蚀刻金属层的方法和使用包括Cl 2 N 2和N 2 N的蚀刻气体的半导体器件的金属化方法。在金属层上形成掩模层，将蚀刻气体供给到金属层，并使用掩模层作为蚀刻掩模，通过蚀刻气体蚀刻金属层。金属层可以由铝或铝合金形成。 Cl 2 N 2和N 2可以1:1至1:10的比例混合。蚀刻气体还可以包括另外的气体，例如包括元素H，O，F，He或C的惰性气体或气体。此外，N 2可以以蚀刻气体总流量的45-65％，这导致半导体器件中的微负载和锥形缺陷的发生减少。

9. 发明申请

US20060293781A1 Method of optimizing seasoning recipe for etch process 审中-公开
公开(公告)号：US20060293781A1
公开(公告)日：2006-12-28
申请号：US11510987
申请日：2006-08-28
申请人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
发明人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
IPC分类号： G06F19/00
CPC分类号： H01L21/67253 , H01L21/32137 , H01L21/67069 , H01L22/20
摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

10. 发明授权

US07118926B2 Method of optimizing seasoning recipe for etch process 失效
标题翻译：优化蚀刻工艺调味配方的方法
公开(公告)号：US07118926B2
公开(公告)日：2006-10-10
申请号：US10652403
申请日：2003-08-29
申请人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
发明人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
IPC分类号： H01L21/00
CPC分类号： H01L21/67253 , H01L21/32137 , H01L21/67069 , H01L22/20
摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.
摘要翻译：一种优化干蚀刻工艺调味配方的方法。该方法包括设置重现性的临界值，主蚀刻配方和初步调味配方。然后使用干蚀刻室中的初步调味配方蚀刻测试晶片。接下来，使用主蚀刻配方对干蚀刻室中的至少10个运行晶片执行主蚀刻处理，并且确定每个晶片的终点检测时间。然后使用确定的终点检测时间确定初始色散和标准偏差。然后将重现性的临界值与初始色散进行比较。如果初始分散度等于或小于再现性的临界值，则使用初步调味配方作为调味配方，否则初步调味配方被修改，重复该过程直到确定最佳调味配方。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式