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1. 发明授权

US08120986B2 Multi-port semiconductor memory device having variable access paths and method therefor 有权
标题翻译：具有可变存取路径的多端口半导体存储器件及其方法
公开(公告)号：US08120986B2
公开(公告)日：2012-02-21
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

2. 发明申请

US20100232249A1 MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR 有权
标题翻译：具有可变存取码的多端口半导体存储器件及其方法
公开(公告)号：US20100232249A1
公开(公告)日：2010-09-16
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

3. 发明授权

US07505353B2 Multi-port semiconductor memory device having variable access paths and method 有权
标题翻译：具有可变存取路径和方法的多端口半导体存储器件
公开(公告)号：US07505353B2
公开(公告)日：2009-03-17
申请号：US11466389
申请日：2006-08-22
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00 , G11C8/12 , G11C8/16 , G11C7/10
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供具有可变存取路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

4. 发明申请

US20070186026A1 System having bus architecture for improving CPU performance and method thereof 审中-公开
标题翻译：具有用于提高CPU性能的总线架构的系统及其方法
公开(公告)号：US20070186026A1
公开(公告)日：2007-08-09
申请号：US11583254
申请日：2006-10-19
申请人： Kyoung-Hwan Kwon
发明人： Kyoung-Hwan Kwon
IPC分类号： G06F13/36
CPC分类号： G06F13/1605 , G06F13/4031
摘要： A system and method for improving the performance of a central processing unit (CPU), in which the system includes a first master such as a CPU, a first local bus connected to a memory device, a bridge, and a main bus connected to a second master and a peripheral device. The bridge is connected among the first master, the memory device, and the main bus and functions as a wrapper and also serves to decode an address output from the first master, monitor a status of ownership of the main bus, and output a wait signal to the first master based on a decoding result and a monitoring result. Accordingly, even while the second master is accessing the peripheral device via the main bus, the first master can access the memory device via the first local bus. The memory device includes a memory core storing predetermined data and a controller having an arbitration function.
摘要翻译：一种用于提高中央处理单元（CPU）的性能的系统和方法，其中系统包括诸如CPU的第一主站，连接到存储设备的第一局部总线，桥接器和连接到CPU的主总线第二主机和外围设备。桥接器连接在第一主机，存储设备和主总线之间，并且用作包装机，并且还用于对从第一主机输出的地址进行解码，监视主总线的所有权状态，并输出等待信号基于解码结果和监视结果到第一主机。因此，即使当第二主机经由主总线访问外围设备时，第一主机可以经由第一本地总线访问存储器设备。存储装置包括存储预定数据的存储器核心和具有仲裁功能的控制器。

5. 发明授权

US09858897B2 Display driver integrated circuit including a plurality of timing controller-embedded drivers for driving a plurality of display regions in synchronization and a display device including the same 有权
公开(公告)号：US09858897B2
公开(公告)日：2018-01-02
申请号：US14955658
申请日：2015-12-01
申请人： Dong-Heon Han , Choong-Bin Kim , Kyoung-Hwan Kwon , Hyun-Sang Park
发明人： Dong-Heon Han , Choong-Bin Kim , Kyoung-Hwan Kwon , Hyun-Sang Park
IPC分类号： G09G3/36 , G09G5/12 , G09G5/00 , G09G5/18 , G09G3/20 , G09G3/3258
CPC分类号： G09G5/12 , G09G3/2088 , G09G3/3258 , G09G3/3666 , G09G5/006 , G09G5/18 , G09G2310/0264 , G09G2310/0278 , G09G2310/08 , G09G2330/022
摘要： A display device includes at least one display panel and a display driver integrated circuit (DDI). The at least one display panel includes a first display region and a second display region. The DDI includes a first timing controller-embedded driver (TED) and a second TED. The first TED is configured to process a first image data to provide a first display data to the first display region and the second TED is configured to process a second image data to provide a second display data to the second display region. The first TED is configured to control display timings of the first display data and the second display data.

6. 发明授权

US08477543B2 Data input circuit with a valid strobe signal generation circuit 有权
标题翻译：具有有效选通信号发生电路的数据输入电路
公开(公告)号：US08477543B2
公开(公告)日：2013-07-02
申请号：US13051060
申请日：2011-03-18
申请人： Kyoung-Hwan Kwon
发明人： Kyoung-Hwan Kwon
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093
摘要： A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.
摘要翻译：数据输入电路包括有效的选通信号产生电路和数据选通信号计数器。有效选通信号产生电路被配置为去除产生的内部选通信号的脉冲并产生有效的选通信号。脉冲可能在前导码期间产生。数据选通信号计数器被配置为根据突发长度信息对有效的选通信号进行计数，并且在写入操作时产生用于对准数据的写入锁存信号。

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