专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07772671B2 Semiconductor device having an element isolating insulating film 有权
标题翻译：具有元件隔离绝缘膜的半导体器件
公开(公告)号：US07772671B2
公开(公告)日：2010-08-10
申请号：US12068635
申请日：2008-02-08
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L29/00
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.
摘要翻译：一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

2. 发明申请

US20080224252A1 Semiconductor device having an element isolating insulating film 有权
标题翻译：具有元件隔离绝缘膜的半导体器件
公开(公告)号：US20080224252A1
公开(公告)日：2008-09-18
申请号：US12068635
申请日：2008-02-08
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L29/00
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
摘要翻译：在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸，以防止形成小平面。随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

3. 发明授权

US06989316B2 Semiconductor device and method for manufacturing 失效
公开(公告)号：US06989316B2
公开(公告)日：2006-01-24
申请号：US10406281
申请日：2003-04-04
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L21/20
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

4. 发明授权

US06617226B1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06617226B1
公开(公告)日：2003-09-09
申请号：US09609107
申请日：2000-06-30
申请人： Kyoioni Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoioni Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L2120
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
摘要翻译：在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸，以防止形成小平面。随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

5. 发明申请

US20050006637A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20050006637A1
公开(公告)日：2005-01-13
申请号：US10743006
申请日：2003-12-23
申请人： Toshihiko Iinuma , Ichiro Mizushima , Mitsuaki Izuha , Kiyotaka Miyano , Kyoichi Suguro
发明人： Toshihiko Iinuma , Ichiro Mizushima , Mitsuaki Izuha , Kiyotaka Miyano , Kyoichi Suguro
IPC分类号： H01L21/28 , H01L21/336 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/06
CPC分类号： H01L29/66477 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.

6. 发明授权

US06924518B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06924518B2
公开(公告)日：2005-08-02
申请号：US10743006
申请日：2003-12-23
申请人： Toshihiko Iinuma , Ichiro Mizushima , Mitsuaki Izuha , Kiyotaka Miyano , Kyoichi Suguro
发明人： Toshihiko Iinuma , Ichiro Mizushima , Mitsuaki Izuha , Kiyotaka Miyano , Kyoichi Suguro
IPC分类号： H01L21/28 , H01L21/336 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/80
CPC分类号： H01L29/66477 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.
摘要翻译：公开了一种半导体器件，其包括半导体衬底，形成在半导体衬底内以限定有源区的隔离区，在元件区内以从隔离区升高的表面形成的一对杂质扩散区， SiGe膜形成在杂质扩散区域的上表面上，以部分地覆盖杂质扩散区域的侧表面，SiGe膜的Ge浓度在SiGe膜的下表面处比在 SiGe膜，形成在SiGe膜上的金属硅化物层，以及形成在半导体衬底的有源区中的栅电极，栅极绝缘膜插入其间并且具有形成在侧表面上的侧壁绝缘膜。

7. 发明授权

US06893928B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06893928B2
公开(公告)日：2005-05-17
申请号：US10390046
申请日：2003-03-18
申请人： Tsutomu Sato , Ichiro Mizushima , Yoshitaka Tsunashima , Toshihiko Iinuma , Kiyotaka Miyano
发明人： Tsutomu Sato , Ichiro Mizushima , Yoshitaka Tsunashima , Toshihiko Iinuma , Kiyotaka Miyano
IPC分类号： H01L29/78 , H01L21/324 , H01L21/336 , H01L21/762 , H01L29/06 , H01L29/786
CPC分类号： H01L29/66583 , H01L21/324 , H01L21/76229 , H01L21/76232 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/42356 , H01L29/66651 , H01L29/78 , H01L29/7831 , H01L29/78639
摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
摘要翻译：在硅衬底的位于MOS晶体管的沟道区之下的部分提供空腔。

8. 发明授权

US06335251B1 Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor 有权
公开(公告)号：US06335251B1
公开(公告)日：2002-01-01
申请号：US09824215
申请日：2001-04-03
申请人： Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Tomohiro Saito
发明人： Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Tomohiro Saito
IPC分类号： H01L21336
摘要： A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate. A second gate-side-wall insulating film is formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film. The portion formed on the bottom surface exists in an inner bottom surface portion of the bottom surface of the first gate-sidewall insulating film adjacent to the gate electrode. The elevated source film and the elevated drain film are free from any facet in portions made contact with the first gate-side-wall insulating film.

9. 发明授权

US06570217B1 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06570217B1
公开(公告)日：2003-05-27
申请号：US09296669
申请日：1999-04-22
申请人： Tsutomu Sato , Ichiro Mizushima , Yoshitaka Tsunashima , Toshihiko Iinuma , Kiyotaka Miyano
发明人： Tsutomu Sato , Ichiro Mizushima , Yoshitaka Tsunashima , Toshihiko Iinuma , Kiyotaka Miyano
IPC分类号： H01L2926
CPC分类号： H01L29/66583 , H01L21/324 , H01L21/76229 , H01L21/76232 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/42356 , H01L29/66651 , H01L29/78 , H01L29/7831 , H01L29/78639
摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

10. 发明授权

US06232641B1 Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor 有权
标题翻译：具有升高的源极和漏极结构的半导体器件及其制造方法
公开(公告)号：US06232641B1
公开(公告)日：2001-05-15
申请号：US09321846
申请日：1999-05-28
申请人： Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Tomohiro Saito
发明人： Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Tomohiro Saito
IPC分类号： H01L31119
CPC分类号： H01L29/66628 , H01L29/66545
摘要： A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate. A second gate-side-wall insulating film is formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film. The portion formed on the bottom surface exists in an inner bottom surface portion of the bottom surface of the first gate-side-wall insulating film adjacent to the gate electrode. The elevated source film and the elevated drain film are free from any facet in portions made contact with the first gate-side-wall insulating film.
摘要翻译：形成具有升高的源极和漏极结构的MOS晶体管的半导体器件被布置成具有通过绝缘膜形成在硅衬底的表面上的栅电极。在硅的表面上的源极区域和漏极区域上形成有在硅衬底的表面上导电且升高的至少一层由金属硅化物膜构成的表面部分的升高的源极膜和升高的漏极膜基质。因此，形成具有使源极区域和漏极区域的表面在硅衬底的表面上升高的结构的MOS晶体管。第一栅极侧壁绝缘膜形成在MOS晶体管的栅电极的侧壁上，并且具有与硅衬底的表面分开形成的底表面。在第一栅极侧壁绝缘膜和栅电极之间以及第一栅极侧壁绝缘膜的底面上形成第二栅极侧壁绝缘膜。形成在底表面上的部分存在于与栅电极相邻的第一栅极侧壁绝缘膜的底表面的内底表面部分中。升高的源极膜和升高的漏极膜在与第一栅极侧壁绝缘膜接触的部分中没有任何刻面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式