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1. 发明申请

US20050162964A1 Dynamic semiconductor memory device and power saving mode of operation method of the same 失效
标题翻译：动态半导体存储器件和省电模式的操作方法相同
公开(公告)号：US20050162964A1
公开(公告)日：2005-07-28
申请号：US11015391
申请日：2004-12-16
申请人： Kye-Hyun Kyung , Kyu-Han Han
发明人： Kye-Hyun Kyung , Kyu-Han Han
IPC分类号： G11C5/00 , G11C7/00 , G11C8/08 , G11C8/18 , G11C11/406 , G11C11/408
CPC分类号： G11C11/4087 , G11C8/08 , G11C8/18 , G11C11/406 , G11C2211/4067
摘要： A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.
摘要翻译：动态半导体存储器件包括存储单元阵列，其包括连接在多个字线和多个位线对之间的多个存储单元。模式设置部分接收从外部部分施加的模式设置代码，以响应于模式设置命令产生用于功率节省模式的功率节省模式控制信号。在正常模式操作期间，地址控制部分对从外部施加的地址或刷新地址进行解码以选择多个字线中的一个。地址控制部分还在省电操作模式期间选择地址的预定数量的位。因此，半导体存储器件延长刷新周期，同时减少刷新时间，导致更低的功耗。

2. 发明授权

US07167407B2 Dynamic semiconductor memory device and power saving mode of operation method of the same 失效
标题翻译：动态半导体存储器件和省电模式的操作方法相同
公开(公告)号：US07167407B2
公开(公告)日：2007-01-23
申请号：US11015391
申请日：2004-12-16
申请人： Kye-Hyun Kyung , Kyu-Han Han
发明人： Kye-Hyun Kyung , Kyu-Han Han
IPC分类号： G11C7/00
CPC分类号： G11C11/4087 , G11C8/08 , G11C8/18 , G11C11/406 , G11C2211/4067
摘要： A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.
摘要翻译：动态半导体存储器件包括存储单元阵列，其包括连接在多个字线和多个位线对之间的多个存储单元。模式设置部分接收从外部部分施加的模式设置代码，以响应于模式设置命令产生用于功率节省模式的功率节省模式控制信号。在正常模式操作期间，地址控制部分对从外部施加的地址或刷新地址进行解码以选择多个字线中的一个。地址控制部分还在省电操作模式期间选择地址的预定数量的位。因此，半导体存储器件延长刷新周期，同时减少刷新时间，导致更低的功耗。

3. 发明授权

US07459957B2 Fuse circuit with leakage path elimination 失效
标题翻译：保险丝电路具有泄漏路径消除
公开(公告)号：US07459957B2
公开(公告)日：2008-12-02
申请号：US11565838
申请日：2006-12-01
申请人： Min-Soo Kim , Kyu-Han Han
发明人： Min-Soo Kim , Kyu-Han Han
IPC分类号： H01H37/76
CPC分类号： G01R31/3004 , G01R31/31717 , G01R31/3172
摘要： A fuse circuit may include a fuse cut detection unit to output state information indicating whether or not a fuse is cut during a fuse cut detection time period, a maintenance and output unit to maintain the state information and output a fuse state information signal, and a connection/disconnection unit to connect the fuse cut detection unit to the maintenance and output unit during the fuse cut detection time period and disconnect the fuse cut detection unit from the maintenance and output unit after the fuse cut detection time period. A fuse circuit may recognize an indefinite voltage at a detection node caused by a leakage path through a fuse as a predetermined fuse state.
摘要翻译：保险丝电路可以包括熔丝切断检测单元，用于输出表示在保险丝切断检测时间段期间保险丝是否切断的状态信息，维持和输出单元以维持状态信息并输出保险丝状态信息信号，以及连接/断开单元，在保险丝断开检测时间段内将保险丝切断检测单元连接到维护和输出单元，并在保险丝断开检测时间段之后断开保险丝切断检测单元与维护和输出单元的连接。熔丝电路可以识别由作为预定熔丝状态的通过熔丝的泄漏路径引起的检测节点处的不确定电压。

4. 发明授权

US5926426A Semiconductor memory device with single-cycle internal read/write function 失效
标题翻译：具有单周期内部读/写功能的半导体存储器件
公开(公告)号：US5926426A
公开(公告)日：1999-07-20
申请号：US865385
申请日：1997-05-29
申请人： Kyu-Han Han
发明人： Kyu-Han Han
IPC分类号： G11C11/401 , G09G5/00 , G11C7/00 , G11C7/10 , G11C11/407
CPC分类号： G11C7/00 , G11C7/1006
摘要： A semiconductor memory device having a single-cycle internal read/write function provides data relocation at high speed. Data is read from a first or source address location and then transferred directly from the sense amps to write drivers for writing to a destination address without latching in the interim. Accordingly, chip area is reduced by elimination of the I/O latch circuits. Since both the data read and write operations are performed during one cycle time, the cycle time is reduced while the bandwidth is increased. The invention has particular application to frame buffer memories and the like.
摘要翻译：具有单周期内部读/写功能的半导体存储器件提供高速数据重定位。数据从第一个或第一个源地址读取，然后直接从感测放大器传输到写入驱动程序以写入到目标地址，而不会暂时锁定。因此，通过消除I / O锁存电路来减少芯片面积。由于在一个周期时间内执行数据读取和写入操作，所以在带宽增加的同时减少周期时间。本发明特别适用于帧缓冲存储器等。

5. 发明授权

US5682351A Semiconductor memory device having an internal copy function 失效
标题翻译：具有内部复制功能的半导体存储器件
公开(公告)号：US5682351A
公开(公告)日：1997-10-28
申请号：US680572
申请日：1996-07-12
申请人： Kyu-Han Han
发明人： Kyu-Han Han
IPC分类号： G11C11/41 , G11C7/00 , G11C11/401 , G11C8/00
CPC分类号： G11C7/00
摘要： A semiconductor memory device having an internal copy function. The memory device includes a memory cell array composed of a plurality of memory cells coupled to a plurality of bit lines, a plurality of column selectors coupled between the bit lines and an input/output data line for being turned on in response to a column select signal, a data amplifying circuit coupled to the input/output data line for amplifying the readout data, a data storage for receiving and latching the amplified data, and a write driver for outputting the latched data to the input/output data line.
摘要翻译：一种具有内部复制功能的半导体存储器件。存储器件包括由耦合到多个位线的多个存储器单元组成的存储器单元阵列，耦合在位线之间的多个列选择器和用于响应于列选择而导通的输入/输出数据线信号，耦合到用于放大读出数据的输入/输出数据线的数据放大电路，用于接收和锁存放大数据的数据存储器，以及用于将锁存数据输出到输入/输出数据线的写入驱动器。

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