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1. 发明授权

US5693555A Method for fabricating BiCMOS device 失效
标题翻译： BiCMOS器件制造方法
公开(公告)号：US5693555A
公开(公告)日：1997-12-02
申请号：US670756
申请日：1996-06-21
申请人： Kwang-Soo Kim , Cheon-Soo Kim , Kyu-Ha Baek , Bo-Woo Kim
发明人： Kwang-Soo Kim , Cheon-Soo Kim , Kyu-Ha Baek , Bo-Woo Kim
IPC分类号： H01L21/822 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A method for fabricating a bipolar complementary metal oxide semiconductor device, includes a first step of forming a three-layered substrate of p.sup.- /n.sup.+ /n.sup.- type or n.sup.- /p.sup.+ /p.sup.- type and forming p- and n-wells to be adjacent to each other to the bottom of the top layer of the three-layered substrate; a second step of isolating the p- and n-wells from each other and defining a region for a bipolar transistor on one side to separate base/emitter regions from each other; a third step of defining a gate region to form a metal- oxide semiconductor transistor in each of the p- and n-wells and forming collector/emitter regions in the bipolar transistor region; and a fourth step of forming an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor and a bipolar transistor on the p-well, n-well and collector/emitter regions, respectively, and forming source/drain and base electrodes through diffusion by using a doped polycrystalline silicon sidewall spacer.
摘要翻译：一种制造双极互补金属氧化物半导体器件的方法，包括：形成p / n + / n型或n / p + / p-型三层衬底并形成p-和n-阱的第一步骤彼此相邻到三层基板的顶层的底部; 将p阱和n阱彼此隔离并且在一侧限定双极晶体管的区域以将基极/发射极区彼此分离的第二步骤; 限定栅极区以在所述p阱和n阱中的每一个中形成金属氧化物半导体晶体管并在所述双极晶体管区域中形成集电极/发射极区域的第三步骤; 以及分别在p阱，n阱和集电极/发射极区域上形成n型金属氧化物半导体晶体管，p型金属氧化物半导体晶体管和双极晶体管的第四步骤，并且形成源极/漏极和通过使用掺杂的多晶硅侧壁间隔物扩散基底电极。

2. 发明授权

US08939079B2 First printing plate and second printing plate 有权
标题翻译：第一印版和第二印版
公开(公告)号：US08939079B2
公开(公告)日：2015-01-27
申请号：US13300689
申请日：2011-11-21
申请人： Joo Yeon Kim , Kyu-Ha Baek , Lee Mi Do , Ji Man Park , Kunsik Park , Zin Sig Kim , Dong-Pyo Kim , Ye Sul Jeong
发明人： Joo Yeon Kim , Kyu-Ha Baek , Lee Mi Do , Ji Man Park , Kunsik Park , Zin Sig Kim , Dong-Pyo Kim , Ye Sul Jeong
IPC分类号： B41N1/00 , B29D11/00 , G02B5/08
CPC分类号： B41N1/00 , B29D11/00596 , G02B5/0816 , Y10T29/49
摘要： Disclosed are a printing plate and a mirror thereof, the printing plate including: printing portions for transferring an immersed solution, the printing portions being formed flat and arranged at regular intervals on one side of an upper part of the printing plate; and non-printing portions corresponding to a remaining area other than the printing portions, the non-printing portions being formed with at least two concavities and convexities respectively and arranged at regular intervals on the other side of the upper part of the printing plate.
摘要翻译：公开了一种印版及其反射镜，印版包括：用于转印浸液的印刷部分，印刷部分在印版的上部一侧上以规则的间隔形成为平坦的; 以及对应于除了印刷部分之外的其余区域的非印刷部分，非印刷部分分别形成有至少两个凹凸，并且在印版的上部的另一侧上以规则的间隔布置。

3. 发明授权

US08404588B2 Method of manufacturing via electrode 有权
标题翻译：通孔电极的制造方法
公开(公告)号：US08404588B2
公开(公告)日：2013-03-26
申请号：US13267215
申请日：2011-10-06
申请人： Dong-Pyo Kim , Kyu-Ha Baek , Kunsik Park , Ji Man Park , Zin Sig Kim , Joo Yeon Kim , Ye Sul Jeong , Lee-Mi Do
发明人： Dong-Pyo Kim , Kyu-Ha Baek , Kunsik Park , Ji Man Park , Zin Sig Kim , Joo Yeon Kim , Ye Sul Jeong , Lee-Mi Do
IPC分类号： H01L21/44
CPC分类号： B82Y40/00 , B82Y30/00 , H01L21/288 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles.
摘要翻译：提供一种制造通孔电极的方法，通过该方法可以增加或最大化生产率和产量。本发明的方法包括：在基板上形成通孔; 在所述通孔的侧壁和底部形成催化剂层; 以及通过将催化剂层暴露于与石墨烯颗粒混合的溶液而在通孔中形成石墨烯层。

4. 发明申请

US20120086132A1 METHOD OF MANUFACTURING VIA ELECTRODE 有权
标题翻译：通过电极制造的方法
公开(公告)号：US20120086132A1
公开(公告)日：2012-04-12
申请号：US13267215
申请日：2011-10-06
申请人： Dong-Pyo Kim , Kyu-Ha Baek , Kunsik Park , Ji Man Park , Zin Sig Kim , Joo Yeon Kim , Ye Sul Jeong , Lee-Mi Do
发明人： Dong-Pyo Kim , Kyu-Ha Baek , Kunsik Park , Ji Man Park , Zin Sig Kim , Joo Yeon Kim , Ye Sul Jeong , Lee-Mi Do
IPC分类号： H01L23/48 , H01L21/02 , H01L21/768 , B82Y40/00 , B82Y99/00
CPC分类号： B82Y40/00 , B82Y30/00 , H01L21/288 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles.
摘要翻译：提供一种制造通孔电极的方法，通过该方法可以增加或最大化生产率和产量。本发明的方法包括：在基板上形成通孔; 在通孔的侧壁和底部形成催化剂层; 以及通过将催化剂层暴露于与石墨烯颗粒混合的溶液而在通孔中形成石墨烯层。

5. 发明授权

US07998862B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07998862B2
公开(公告)日：2011-08-16
申请号：US12689344
申请日：2010-01-19
申请人： Kunsik Park , Kyu-Ha Baek , Lee-Mi Do , Dong-Pyo Kim , Ji Man Park
发明人： Kunsik Park , Kyu-Ha Baek , Lee-Mi Do , Dong-Pyo Kim , Ji Man Park
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76898 , H01L21/2885
摘要： A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底中形成通孔，在通孔的内侧形成隔离层，在半导体衬底的上部和通孔的内侧形成扩散阻挡层形成隔离层的孔，在形成有扩散阻挡层的半导体衬底上布置含有带电荷的金属颗粒的溶剂，并通过使用外力移动金属颗粒来填充通孔。所施加的外力包括导致电流在半导体衬底和溶剂之间流动的电压，施加在半导体衬底和溶剂之间的电场或施加在半导体衬底和溶剂之间的磁场。

6. 发明授权

US08143670B2 Self aligned field effect transistor structure 有权
标题翻译：自对准场效应晶体管结构
公开(公告)号：US08143670B2
公开(公告)日：2012-03-27
申请号：US12619116
申请日：2009-11-16
申请人： Lee-Mi Do , Kyu-Ha Baek
发明人： Lee-Mi Do , Kyu-Ha Baek
IPC分类号： H01L29/76
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/66537 , H01L29/66545 , H01L29/66575
摘要： Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.
摘要翻译：提供了自对准的场效应晶体管结构。自对准场效应晶体管结构包括：衬底上的有源区; 活动区域上的U形栅绝缘图案; 以及通过栅极绝缘图案自对准并设置在栅极绝缘图案的内部空间中的栅电极。

7. 发明申请

US20110104322A1 TEMPLATES USED FOR NANOIMPRINT LITHOGRAPHY AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：用于纳米压印的模板及其制作方法
公开(公告)号：US20110104322A1
公开(公告)日：2011-05-05
申请号：US12763380
申请日：2010-04-20
申请人： Kunsik PARK , Dong-Pyo Kim , Ji Man Park , Kyu-Ha Baek , Lee-Mi Do
发明人： Kunsik PARK , Dong-Pyo Kim , Ji Man Park , Kyu-Ha Baek , Lee-Mi Do
IPC分类号： B28B11/08 , B05D3/10
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Provided are a template used for nanoimprint lithography and a method for fabricating the same. A raised first deposition layer pattern including at least one downwardly sloped side surface is formed on a substrate. A second deposition layer pattern covering the side surface of the raised first deposition layer pattern and progressively decreasing in width downward along the side surface of the raised first deposition layer pattern is formed. A third deposition layer is formed on the entire surface of a structure on which the second deposition layer pattern. A second deposition layer nano pattern between the raised first deposition layer pattern and a planarized third deposition layer is formed by planarizing the third deposition layer to expose upper surfaces of the raised first deposition layer pattern and the second deposition layer pattern. An intaglio nano pattern defined by side surfaces sloped downward from upper surfaces of the raised first deposition layer pattern and the planarized third deposition layer to the surface of the substrate is formed by removing the second deposition layer nano pattern.
摘要翻译：提供了用于纳米压印光刻的模板及其制造方法。在衬底上形成包括至少一个向下倾斜的侧表面的升高的第一沉积层图案。形成覆盖凸起的第一沉积层图案的侧表面并且沿着凸起的第一沉积层图案的侧表面沿着宽度逐渐减小的第二沉积层图案。第三沉积层形成在其上具有第二沉积层图案的结构的整个表面上。在凸起的第一沉积层图案和平坦化的第三沉积层之间的第二沉积层纳米图案通过平坦化第三沉积层以暴露升高的第一沉积层图案和第二沉积层图案的上表面而形成。通过去除第二沉积层纳米图案，形成由从凸起的第一沉积层图案的上表面向下倾斜的侧表面和平坦化的第三沉积层到基板的表面限定的凹版纳米图案。

8. 发明申请

US20100155793A1 SELF ALIGNED FIELD EFFECT TRANSISTOR STRUCTURE 有权
标题翻译：自对准场效应晶体管结构
公开(公告)号：US20100155793A1
公开(公告)日：2010-06-24
申请号：US12619116
申请日：2009-11-16
申请人： Lee-Mi DO , Kyu-Ha Baek
发明人： Lee-Mi DO , Kyu-Ha Baek
IPC分类号： H01L29/78
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/66537 , H01L29/66545 , H01L29/66575
摘要： Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.
摘要翻译：提供了自对准的场效应晶体管结构。自对准场效应晶体管结构包括：衬底上的有源区; 活动区域上的U形栅绝缘图案; 以及通过栅极绝缘图案自对准并设置在栅极绝缘图案的内部空间中的栅电极。

9. 发明授权

US08324689B2 Self aligned field effect transistor structure 有权
标题翻译：自对准场效应晶体管结构
公开(公告)号：US08324689B2
公开(公告)日：2012-12-04
申请号：US12635661
申请日：2009-12-10
申请人： Lee-Mi Do , Kyu-Ha Baek
发明人： Lee-Mi Do , Kyu-Ha Baek
IPC分类号： H01L29/66
CPC分类号： H01L29/785 , H01L27/1292 , H01L29/41791 , H01L29/66795 , H01L51/0554
摘要： Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode connected to the active region pattern and disposed to be symmetric with respect to a line connecting the first and second gate electrodes, wherein the first and second gate electrodes and the source and drain electrodes are disposed on the same plane of the substrate.
摘要翻译：提供了自对准场效应晶体管结构。自对准场效应晶体管结构包括：衬底上的有源区图案; 第一栅极电极和第二栅极电极，其间具有有源区域图案; 以及源极电极和漏电极，连接到有源区域图案并且被设置为相对于连接第一和第二栅电极的线对称，其中第一和第二栅电极以及源电极和漏极彼此配置基板的平面。

10. 发明申请

US20120140350A1 PRINTING PLATE AND MIRROR THEREOF 有权
标题翻译：印版及其镜像
公开(公告)号：US20120140350A1
公开(公告)日：2012-06-07
申请号：US13300689
申请日：2011-11-21
申请人： Joo Yeon Kim , Kyu-Ha Baek , Lee Mi Do , Ji Man Park , Kunsik Park , Zin Sig Kim , Dong-Pyo Kim , Ye Sul Jeong
发明人： Joo Yeon Kim , Kyu-Ha Baek , Lee Mi Do , Ji Man Park , Kunsik Park , Zin Sig Kim , Dong-Pyo Kim , Ye Sul Jeong
IPC分类号： B41N1/12 , G02B5/08 , B23P17/00
CPC分类号： B41N1/00 , B29D11/00596 , G02B5/0816 , Y10T29/49
摘要： Disclosed are a printing plate and a mirror thereof, the printing plate including: printing portions for transferring an immersed solution, the printing portions being formed flat and arranged at regular intervals on one side of an upper part of the printing plate; and non-printing portions corresponding to a remaining area other than the printing portions, the non-printing portions being formed with at least two concavities and convexities respectively and arranged at regular intervals on the other side of the upper part of the printing plate.
摘要翻译：公开了一种印版及其反射镜，印版包括：用于转印浸液的印刷部分，印刷部分在印版的上部一侧上以规则的间隔形成为平坦的; 以及对应于除了印刷部分之外的其余区域的非印刷部分，非印刷部分分别形成有至少两个凹凸，并且在印版的上部的另一侧上以规则的间隔布置。

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