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1. 发明授权

US07492032B2 Fuse regions of a semiconductor memory device and methods of fabricating the same 有权
标题翻译：半导体存储器件的保险丝区域及其制造方法
公开(公告)号：US07492032B2
公开(公告)日：2009-02-17
申请号：US11108636
申请日：2005-04-19
申请人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
发明人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
摘要翻译：公开了一种制造熔丝区域的装置和方法。熔丝区域可以包括形成在衬底上的层间绝缘层，设置在层间绝缘层上的多个熔丝以及位于保险丝之间的熔断器隔离壁，其中每个保险丝隔离壁可以包括下部和上部熔丝隔离图案。

2. 发明申请

US20050236688A1 Fuse regions of a semiconductor memory device and methods of fabricating the same 有权
标题翻译：半导体存储器件的保险丝区域及其制造方法
公开(公告)号：US20050236688A1
公开(公告)日：2005-10-27
申请号：US11108636
申请日：2005-04-19
申请人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
发明人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
IPC分类号： H01L21/82 , G11C17/16 , H01L21/4763 , H01L21/768 , H01L21/8246 , H01L23/525 , H01L27/112 , H01L29/40
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
摘要翻译：公开了一种制造熔丝区域的装置和方法。熔丝区域可以包括形成在衬底上的层间绝缘层，设置在层间绝缘层上的多个熔丝以及位于保险丝之间的熔断器隔离壁，其中每个保险丝隔离壁可以包括下部和上部熔丝隔离图案。

3. 发明申请

US20060214260A1 Semiconductor device having fuse pattern and methods of fabricating the same 失效
公开(公告)号：US20060214260A1
公开(公告)日：2006-09-28
申请号：US11387158
申请日：2006-03-22
申请人： Tai-Heui Cho , Kun-Gu Lee
发明人： Tai-Heui Cho , Kun-Gu Lee
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

4. 发明授权

US07556989B2 Semiconductor device having fuse pattern and methods of fabricating the same 失效
标题翻译：具有熔丝图案的半导体器件及其制造方法
公开(公告)号：US07556989B2
公开(公告)日：2009-07-07
申请号：US11387158
申请日：2006-03-22
申请人： Tai-Heui Cho , Kun-Gu Lee
发明人： Tai-Heui Cho , Kun-Gu Lee
IPC分类号： H01L21/82 , H01L21/311
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.
摘要翻译：半导体器件包括具有熔丝区域和互连区域的半导体衬底，形成在熔丝区域和互连区域中的第一绝缘层，形成在熔丝区域中的第一绝缘层上的熔丝图案，熔丝图案包括第一导电图案和第一封盖图案，形成在互连区域中的第一绝缘层上的互连图案，包括第二导电图案和第二封盖图案，并且具有大于熔丝图案的厚度的厚度，以及第二绝缘体层，形成在第一绝缘层上并覆盖熔丝图案。

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