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1. 发明授权

US07881145B2 Semiconductor device and semiconductor system having the same 有权
标题翻译：半导体器件和具有该半导体器件的半导体系统
公开(公告)号：US07881145B2
公开(公告)日：2011-02-01
申请号：US12453872
申请日：2009-05-26
申请人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
发明人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C7/22 , G11C8/12 , G11C13/0004 , G11C2013/0076 , G11C2207/2209
摘要： A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.
摘要翻译：根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

2. 发明授权

US08189422B2 Semiconductor device and semiconductor system having the same 有权
标题翻译：半导体器件和具有该半导体器件的半导体系统
公开(公告)号：US08189422B2
公开(公告)日：2012-05-29
申请号：US12929123
申请日：2011-01-03
申请人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
发明人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C7/22 , G11C8/12 , G11C13/0004 , G11C2013/0076 , G11C2207/2209
摘要： A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.
摘要翻译：根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

3. 发明申请

US20110096611A1 Semiconductor device and semiconductor system having the same 有权
公开(公告)号：US20110096611A1
公开(公告)日：2011-04-28
申请号：US12929123
申请日：2011-01-03
申请人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
发明人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/22 , G11C8/12 , G11C13/0004 , G11C2013/0076 , G11C2207/2209
摘要： A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

4. 发明申请

US20090303807A1 Semiconductor device and semiconductor system having the same 有权
标题翻译：半导体器件和具有该半导体器件的半导体系统
公开(公告)号：US20090303807A1
公开(公告)日：2009-12-10
申请号：US12453872
申请日：2009-05-26
申请人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
发明人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C7/22 , G11C8/12 , G11C13/0004 , G11C2013/0076 , G11C2207/2209
摘要： A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.
摘要翻译：根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

5. 发明授权

US08649204B2 Resistive memory devices and memory systems having the same 有权
标题翻译：具有相同的电阻式存储器件和存储器系统
公开(公告)号：US08649204B2
公开(公告)日：2014-02-11
申请号：US13364942
申请日：2012-02-02
申请人： Joon Min Park , Kwang Jin Lee
发明人： Joon Min Park , Kwang Jin Lee
IPC分类号： G11C11/00
CPC分类号： G11C29/1201 , G11C13/00 , G11C13/0004 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C29/18
摘要： A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.
摘要翻译：非易失性存储器件包括电阻存储器单元阵列和写驱动器，其被配置为以复位电流脉冲驱动阵列中的选定位线，该复位电流脉冲响应于通过第一端子/ 存储器单元重置操作期间的存储器件。所述写入驱动器进一步被配置为按照响应于所述第一外部电压的第一设定电流脉冲和第二设定电流脉冲依次驱动所选位线，所述第二设定电流脉冲响应于通过第二端子输入的第二外部电压 /存储器单元设置操作的焊盘。

6. 发明授权

US08547724B2 Nonvolatile memory device comprising one-time-programmable lock bit register 有权
标题翻译：非易失性存储器件包括一次性可编程锁定位寄存器
公开(公告)号：US08547724B2
公开(公告)日：2013-10-01
申请号：US13032848
申请日：2011-02-23
申请人： Yong-Jun Lee , Kwang Jin Lee , Joon Min Park , Huik Won Seo
发明人： Yong-Jun Lee , Kwang Jin Lee , Joon Min Park , Huik Won Seo
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , G11C11/005 , G11C13/0004 , G11C13/0059 , G11C2211/5641 , G11C2211/5646
摘要： A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.
摘要翻译：非易失性存储器件包括一次性可编程（OTP）锁定位寄存器。非易失性存储器件包括可变电阻存储单元阵列，其包括存储数据的OTP块和存储指示数据是否可更改的OTP锁定状态信息的寄存器。寄存器包括可变存储单元。 OTP锁定状态信息的初始值被设置为程序保护状态。

7. 发明申请

US20120307547A1 RESISTIVE MEMORY DEVICES AND MEMORY SYSTEMS HAVING THE SAME 有权
标题翻译：具有电阻记忆体设备和存储器系统
公开(公告)号：US20120307547A1
公开(公告)日：2012-12-06
申请号：US13364942
申请日：2012-02-02
申请人： Joon Min Park , Kwang Jin Lee
发明人： Joon Min Park , Kwang Jin Lee
IPC分类号： G11C11/00
CPC分类号： G11C29/1201 , G11C13/00 , G11C13/0004 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C29/18
摘要： A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.
摘要翻译：非易失性存储器件包括电阻存储器单元阵列和写驱动器，其被配置为以复位电流脉冲驱动阵列中的选定位线，该复位电流脉冲响应于通过第一端子/ 存储器单元重置操作期间的存储器件。所述写入驱动器被进一步配置为按照响应于所述第一外部电压的第一设定电流脉冲和第二设定电流脉冲依次驱动所选择的位线，所述第二设定电流脉冲响应于通过第二端子输入的第二外部电压 /存储器单元设置操作的焊盘。

8. 发明申请

US20100329070A1 Resistance Semiconductor Memory Device Having Three-Dimensional Stack and Word Line Decoding Method Thereof 有权
标题翻译：具有三维堆栈和字线解码方法的电阻半导体存储器件
公开(公告)号：US20100329070A1
公开(公告)日：2010-12-30
申请号：US12873836
申请日：2010-09-01
申请人： Joon Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

9. 发明申请

US20090279351A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS HAVING CORE STRUCTURES FOR MULTI-WRITING 失效
标题翻译：具有用于多写的核心结构的半导体存储器件和方法
公开(公告)号：US20090279351A1
公开(公告)日：2009-11-12
申请号：US12437438
申请日：2009-05-07
申请人： Joon Min Park , Beak Hyung Cho
发明人： Joon Min Park , Beak Hyung Cho
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C8/10 , G11C7/18 , G11C8/14 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2013/0088 , G11C2213/77
摘要： A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode.
摘要翻译：具有用于多次写入的有效核心结构的半导体存储器件包括数据输入/输出线，多个存储器组，每个存储器组包括多个存储器单元，第一全局位线和第二全局位线，多个存储体，以及分别与数据输入/输出线连接并通过第一和第二全局位线向多个存储体提供编程电流的第一写入驱动器和第二写入驱动器。每个存储体包括与第一全局位线连接的第一单元区域和与第二全局位线连接的第二单元区域。在多写入模式中，同时选择多个存储体中的第一存储体中的第一单元区域和多个存储体之间的第二存储体中的第二单元区域，并将数据写入存储单元中的存储单元选择的第一和第二单元区域，使得在与正常写入模式相同的条件下数据写入时间被减少。

10. 发明授权

US07936594B2 Semiconductor memory devices having core structures for multi-writing 失效
标题翻译：具有用于多写入的核心结构的半导体存储器件
公开(公告)号：US07936594B2
公开(公告)日：2011-05-03
申请号：US12437438
申请日：2009-05-07
申请人： Joon Min Park , Beak Hyung Cho
发明人： Joon Min Park , Beak Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C7/18 , G11C8/14 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2013/0088 , G11C2213/77
摘要： A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode.
摘要翻译：具有用于多次写入的有效核心结构的半导体存储器件包括数据输入/输出线，多个存储器组，每个存储器组包括多个存储器单元，第一全局位线和第二全局位线，多个存储体，以及分别与数据输入/输出线连接并通过第一和第二全局位线向多个存储体提供编程电流的第一写入驱动器和第二写入驱动器。每个存储体包括与第一全局位线连接的第一单元区域和与第二全局位线连接的第二单元区域。在多写入模式中，同时选择多个存储体中的第一存储体中的第一单元区域和多个存储体之间的第二存储体中的第二单元区域，并将数据写入存储单元中的存储单元选择的第一和第二单元区域，使得在与正常写入模式相同的条件下数据写入时间被减少。

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