专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050017285A1 Novel embedded dual-port DRAM process 有权
标题翻译：新型嵌入式双端口DRAM工艺
公开(公告)号：US20050017285A1
公开(公告)日：2005-01-27
申请号：US10920492
申请日：2004-08-18
申请人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis Sinitsky
发明人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis Sinitsky
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译：实现了在集成电路器件中形成DRAM单元的新方法。该方法包括提供基底。在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。沟槽填充有第一介电层。所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。第二电介质层形成在衬底上并衬衬开放的沟槽。沉积覆盖第二介电层并完全填充开放沟槽的导电层。图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

2. 发明授权

US07091543B2 Embedded dual-port DRAM process 有权
标题翻译：嵌入式双端口DRAM工艺
公开(公告)号：US07091543B2
公开(公告)日：2006-08-15
申请号：US10920492
申请日：2004-08-18
申请人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
发明人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译：实现了在集成电路器件中形成DRAM单元的新方法。该方法包括提供基底。在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。沟槽填充有第一介电层。所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。第二电介质层形成在衬底上并衬衬开放的沟槽。沉积覆盖第二介电层并完全填充开放沟槽的导电层。图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

3. 发明授权

US06306767B1 Self-aligned etching method for forming high areal density patterned microelectronic structures 有权
标题翻译：用于形成高密度图案的微电子结构的自对准蚀刻方法
公开(公告)号：US06306767B1
公开(公告)日：2001-10-23
申请号：US09584111
申请日：2000-05-31
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Wen-Chuan Chiang , Ming-Hsiang Chiang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Wen-Chuan Chiang , Ming-Hsiang Chiang
IPC分类号： H01L21302
CPC分类号： H01L27/10888 , H01L21/32139 , H01L27/10811
摘要： Within a method for forming a patterned layer there is first provided a topographic substrate. There is then formed conformally over the topographic substrate a blanket target layer formed of a target material, where the blanket target layer has a lower substantially horizontal portion, an upper substantially horizontal portion and an intermediate portion therebetween. There is then formed upon the lower substantially horizontal portion of the blanket target layer a first masking layer formed of a first masking material and formed upon the upper substantially horizontal portion of the blanket target layer a second masking layer formed of a second masking material. There is then etched, while employing an etch method having an enhanced sequential selectivity for the first masking material and the target material with respect to the second masking material, the first masking layer and the lower substantially horizontal portion of the blanket target layer to form a patterned target layer which leaves exposed a portion of the substrate beneath the lower horizontal portion of the blanket target layer while leaving unetched the upper substantially horizontal portion of the blanket target layer. The method is particularly useful for forming patterned capacitor plate layers.
摘要翻译：在形成图案层的方法中，首先提供地形衬底。然后，在地形基底上形成由目标材料形成的覆盖目标层，其中覆盖层目标层具有下部基本水平的部分，上部基本水平的部分和在其间的中间部分。然后，在覆盖目标层的下部基本水平的部分上形成由第一掩模材料形成并形成在覆盖目标层的上部基本水平的部分上的第一掩蔽层，第二掩蔽层由第二掩蔽材料形成。然后蚀刻，同时采用对于第一掩蔽材料和靶材料相对于第二掩蔽材料具有增强的顺序选择性的蚀刻方法，覆盖目标层的第一掩蔽层和下部基本水平的部分，以形成图案化目标层，其在衬底目标层的下部水平部分的下方露出衬底的一部分，同时保留未覆盖的覆盖目标层的上部基本水平的部分。该方法对于形成图案化电容器板层特别有用。

4. 发明授权

US06794254B1 Embedded dual-port DRAM process 失效
标题翻译：嵌入式双端口DRAM工艺
公开(公告)号：US06794254B1
公开(公告)日：2004-09-21
申请号：US10438646
申请日：2003-05-15
申请人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
发明人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
IPC分类号： H01L21336
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译：实现了在集成电路器件中形成DRAM单元的新方法。该方法包括提供基底。在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。沟槽填充有第一介电层。所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。第二电介质层形成在衬底上并衬衬开放的沟槽。沉积覆盖第二介电层并完全填充开放沟槽的导电层。图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式