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1. 发明申请

US20110220980A1 MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME 有权
标题翻译：带有数字数据线的存储器及其制造方法
公开(公告)号：US20110220980A1
公开(公告)日：2011-09-15
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

2. 发明授权

US08497541B2 Memory having buried digit lines and methods of making the same 有权
标题翻译：具有埋置数字线的存储器和制作相同的方法
公开(公告)号：US08497541B2
公开(公告)日：2013-07-30
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

3. 发明申请

US20060263969A1 Method of manufacturing sidewall spacers on a memory device, and device comprising same 有权
公开(公告)号：US20060263969A1
公开(公告)日：2006-11-23
申请号：US11132472
申请日：2005-05-19
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8244
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

4. 发明授权

US08716116B2 Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline 有权
标题翻译：使用垂直集成的凹槽接入设备和数字线形成DRAM阵列的方法
公开(公告)号：US08716116B2
公开(公告)日：2014-05-06
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

5. 发明申请

US20080119053A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：US20080119053A1
公开(公告)日：2008-05-22
申请号：US12020752
申请日：2008-01-28
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/311
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

6. 发明申请

US20110220994A1 Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline 有权
标题翻译：形成具有垂直集成嵌入式接入设备和数字线的设备的DRAM阵列的方法
公开(公告)号：US20110220994A1
公开(公告)日：2011-09-15
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

7. 发明申请

US20070111436A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：US20070111436A1
公开(公告)日：2007-05-17
申请号：US11616511
申请日：2006-12-27
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

8. 发明申请

US20090315154A1 SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT 有权
标题翻译：具有通孔基板互连的半导体
公开(公告)号：US20090315154A1
公开(公告)日：2009-12-24
申请号：US12142251
申请日：2008-06-19
申请人： Kyle Kirby , Kunal Parekh
发明人： Kyle Kirby , Kunal Parekh
IPC分类号： H01L23/48 , H01L21/768 , H01L21/8234
CPC分类号： H01L21/743 , H01L21/26513 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/49816 , H01L27/0694 , H01L27/10888 , H01L27/10894 , H01L29/66568 , H01L29/78 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548
摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
摘要翻译：描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部金属填充通孔的区域。

9. 发明授权

US07601591B2 Method of manufacturing sidewall spacers on a memory device, and device comprising same 有权
标题翻译：在存储器件上制造侧壁间隔物的方法，以及包括其的装置
公开(公告)号：US07601591B2
公开(公告)日：2009-10-13
申请号：US12020752
申请日：2008-01-28
申请人： David K. Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David K. Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

10. 发明申请

US20070218616A1 Semiconductor constructions, and methods of forming semiconductor constructions 有权
标题翻译：半导体结构以及形成半导体结构的方法
公开(公告)号：US20070218616A1
公开(公告)日：2007-09-20
申请号：US11377094
申请日：2006-03-16
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： H01L21/8234
CPC分类号： H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material.
摘要翻译：本发明包括将部分SOI并入晶体管结构的方法。在特定方面，电介质材料设置在半导体材料上，并被图案化成由间隙分开的至少两个段。然后在电介质材料上并在间隙内生长附加的半导体材料。随后，形成晶体管以在附加半导体材料内包括源极/漏极区域，并且包括在源极/漏极区域之间的沟道。源极/漏极区域中的至少一个主要直接位于电介质材料的一段上，并且沟道不主要直接位于介电材料的任何部分上方。本发明还包括包括对应于电介质材料段的部分SOI的构造，以及主要直接位于介电材料段上的至少一个源/漏区的晶体管，以及不主要直接位于电介质材料的任何段上的沟道。

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